Scott Meninger

Vibration-to-electric energy conversion

A system is proposed to convert ambient mechanical vibration into electrical energy for use in powering autonomous low-power electronic systems. The energy is transduced through the use of a variable capacitor, which has been designed with MEMS (microelectromechanical systems) technology. A low-power controller IC has been fabricated in a 0.6 /spl mu/m CMOS process and has been tested and measured for losses. Based on the tests, the system is expected to produce 8 /spl mu/W of usable power.

A 1-MHZ bandwidth 3.6-GHz 0.18-/spl mu/m CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise

A frequency synthesizer architecture capable of simultaneously achieving high closed-loop bandwidth and low output phase noise is presented. The proposed topology uses a mismatch compensated, hybrid phase/frequency detector and digital-to-analog converter (PFD/DAC) circuit to perform active cancellation of fractional-N quantization noise. When compared to a classical second-order /spl Sigma//spl Delta/ synthesizer, the prototype PFD/DAC synthesizer demonstrates >29 dB quantization noise suppression, without calibration, resulting in a fractional-N synthesizer with 1-MHz closed-loop bandwidth and -155 dBc/Hz phase noise at 20-MHz offset for a 3.6-GHz output. An on-chip band select divider allows the synthesizer to be configured as a dual-band (900 MHz/1.8 GHz) direct modulated transmitter capable of transmitting 271-kb/s GMSK data with less than 3 degrees of rms phase error.

Dual-DLL-based CMOS all-digital temperature sensor for microprocessor thermal monitoring

Todays microprocessors increasingly need on-chip temperature sensors for thermal and power management [1]. Since these sensors do not take part in the main computing activity but rather play the auxiliary, albeit important, role of temperature monitoring, their presence in terms of area, power, and design effort should be minimal, thus, all-digital sensors are desired. Temperature sensing based on temperature-dependent delays of inverters [2] could be suited for microprocessor applications, as it lends itself to digital implementation: by using a time-to-digital converter (TDC), an inverter delay can be compared to an absolute delay reference and converted to a digital temperature output [2] (Fig. 3.7.1). We report on an all-digital CMOS temperature sensor for microprocessor application, which also exploits temperature-dependent inverter delays within the TDC-based framework of Fig. 3.7.1. It, however, has two improvements over prior art of [2]. First, it removes the effect of process variation on inverter delays via calibration at one temperature point (instead of 2-point calibration of [2]), thus, reducing high volume production cost. Second, we use two fine-precision DLLs, one to synthesize a set of temperature-independent delay references in a closed loop, the other as a TDC to compare temperature-dependent inverter delays to the references. The use of DLLs simplifies sensor operation and yields a high measurement bandwidth (5kS/s) at 7b resolution, which could enable fast temperature tracking. This is in contrast to [2], where a counter-based cyclic TDC with an open-loop single delay-reference has a longer measurement time for a similar resolution.

Time-Domain CMOS Temperature Sensors With Dual Delay-Locked Loops for Microprocessor Thermal Monitoring

We report on CMOS temperature sensors that work by measuring temperature-dependent delays in CMOS inverters. Two new features distinguish this work from the prior delay-based temperature sensors. First, our sensor operates with simple, low-cost one-point calibration. Second, it uses delay-locked loops (DLLs) to convert inverter delays to digital temperature outputs: the use of DLLs enables low energy (0.24 μJ/sample) and high bandwidth (5 kilo-samples/s), facilitating fast thermal monitoring. After calibration, measurement errors for 15 chips fabricated in digital CMOS 0.13 μm fall within -4.0~4.0 °C in a temperature range of 0~100 °C, where the temperature chamber used has a control uncertainty of ±1.1 °C. Microprocessor thermal profiling can be a potential application.

A micropower programmable DSP powered using a MEMS-based vibration-to-electric energy converter

An ultra-low-power programmable DSP for sensor applications enables systems to be powered by ambient vibration. The three-chip system consists of a MEMS transducer that converts vibration to a voltage delivered to a conversion IC. The conversion IC creates a stable power supply that provides energy to the sensor DSP load. The system exploits ambient mechanical vibration as its energy source.

A fractional- N frequency synthesizer architecture utilizing a mismatch compensated PFD/DAC structure for reduced quantization-induced phase noise

Techniques are proposed to dramatically reduce the impact of quantization noise in /spl Sigma//spl Delta/ fractional-N synthesizers, thereby improving the existing tradeoff between phase noise and bandwidth that exists in these systems. The key innovation is the introduction of new techniques to overcome nonidealities in a phase-frequency detector (PFD)/digital-to-analog converter (DAC) structure, which combines the functionality of both phase detector and cancellation DAC into a single element. The proposed architecture achieves better gain matching between the phase-error signal and cancellation DAC than offered by previous approaches. Dynamic element matching techniques are introduced to mitigate the effects of PFD/DAC unit element and timing mismatch on synthesizer phase noise performance. We present behavioral simulations of an example application of this technique that demonstrates 36 dB reduction in broad-band quantization-induced phase noise with the use of a 7-b PFD/DAC. Simulations further demonstrate that fractional spurs are rejected to levels <-90 dBc when a low-cost, low-overhead digital gain correction technique is employed.

Bandwidth extension of low noise fractional-N synthesizers

This paper examines issues with extending the bandwidth of fractional-N synthesizers. Quantization noise is shown to be the limiting factor in state-of-the-art fractional-N synthesis. A re-framing of the noise model used to analyze synthesizer phase noise leads directly to a methodology to enable high bandwidth synthesis. We present measured results from a synthesizer based on the proposed methodology that demonstrates >25 dB broadband phase noise reduction compared to a state-of-the-art /spl Sigma//spl Delta/ synthesizer. Finally, we draw conclusions about the future direction of fractional-N synthesis.

A dual band 1.8 GHz/900 MHz, 750 kb/s GMSK transmitter utilizing a hybrid PFD/DAC structure for reduced broadband phase noise

This paper presents the key circuits of a 1 MHz bandwidth, 750 kb/s GMSK transmitter. The fractional-N synthesizer forming the basis of the transmitter uses a combined phase-frequency detector (PFD) and digital-to-analog converter (DAC) circuit element to obtain > 28 dB high frequency noise reduction when compared to classical /spl Sigma//spl Delta/ frequency synthesis. This large reduction in phase noise makes high bandwidth, low noise (-154 dBc/Hz @ 20 MHz offset for 3.565 GHz output) synthesis possible, allowing direct modulation transmission of GMSK data at 750 kb/s.

A 32-core RISC microprocessor with network accelerators, power management and testability features

This paper describes our third generation multicore processor that exhibits a high level of integration. The current design doubles the number of cores, triples the frequency and more than quadruples total memory bandwidth over. It contains 700M transistors and has been fabricated in a 65nm process technology, with 10 layers of copper interconnect and C4 bumps. It contains 32 MIPS cores, 4MB of level 2 cache, multiple hardware accelerator units, 4 72b DDR3 memory controllers operating at 1600 MHz, 20 generic SerDes lanes up to 6.25Gb/s, additional network and boot interfaces and general purpose I/Os. Maximum frequency is 1.6GHz for cores and L2 cache. Excluding I/O, thermal design power ranges from 40W to 65W depending on the frequency bin.