Thucydides Xanthopoulos

The Reliable Router: A Reliable and High-Performance Communication Substrate for Parallel Computers

The Reliable Router (RR) is a network switching element targeted to two-dimensional mesh interconnection network topologies. It is designed to run at 100 MHz and reach a useful link bandwidth of 3.2 Gbit/sec. The Reliable Router uses adaptive routing coupled with link-level retransmission and a unique-token protocol to increase both performance and reliability. The RR can handle a single node or link failure anywhere in the network without interruption of service. Other unique features include a queueless low-latency plesiochronous channel interface, and simultaneous bidirectional signalling.

The design and analysis of the clock distribution network for a 1.2 GHz Alpha microprocessor

Single-wire, synchronous clocking systems for increasingly large and complex microprocessors present major technical challenges: Die size increases whereas target clock skew and jitter typically remain a constant percentage of a decreasing cycle time. The clocking methodology of the present Alpha microprocessor handles such challenges by radically departing from a single chip-wide clock distribution, to better control clock skew, jitter and power dissipation. Four major clocks (one reference and three derived) are used to clock separate chip sections.

Dual-DLL-based CMOS all-digital temperature sensor for microprocessor thermal monitoring

Todays microprocessors increasingly need on-chip temperature sensors for thermal and power management [1]. Since these sensors do not take part in the main computing activity but rather play the auxiliary, albeit important, role of temperature monitoring, their presence in terms of area, power, and design effort should be minimal, thus, all-digital sensors are desired. Temperature sensing based on temperature-dependent delays of inverters [2] could be suited for microprocessor applications, as it lends itself to digital implementation: by using a time-to-digital converter (TDC), an inverter delay can be compared to an absolute delay reference and converted to a digital temperature output [2] (Fig. 3.7.1). We report on an all-digital CMOS temperature sensor for microprocessor application, which also exploits temperature-dependent inverter delays within the TDC-based framework of Fig. 3.7.1. It, however, has two improvements over prior art of [2]. First, it removes the effect of process variation on inverter delays via calibration at one temperature point (instead of 2-point calibration of [2]), thus, reducing high volume production cost. Second, we use two fine-precision DLLs, one to synthesize a set of temperature-independent delay references in a closed loop, the other as a TDC to compare temperature-dependent inverter delays to the references. The use of DLLs simplifies sensor operation and yields a high measurement bandwidth (5kS/s) at 7b resolution, which could enable fast temperature tracking. This is in contrast to [2], where a counter-based cyclic TDC with an open-loop single delay-reference has a longer measurement time for a similar resolution.

Architecture and implementation of the reliable router

Abstract The Reliable Router (RR) is a network switching element targeted to two-dimensional mesh interconnection network topologies. It is designed to run at 100 MHz and reach a useful link bandwidth of 3.2 Gbitlsec. The Reliable Router uses adaptive routing coupled with link-level retransmission and a unique-token protocol to increase both performance and reliability. The RR can handle a single node or link failure anywhere in the network without in terruption of service. Other unique features include a queueless low-latency plesiochronous channel inter face and simultaneous bidirectional signalling.

Time-Domain CMOS Temperature Sensors With Dual Delay-Locked Loops for Microprocessor Thermal Monitoring

We report on CMOS temperature sensors that work by measuring temperature-dependent delays in CMOS inverters. Two new features distinguish this work from the prior delay-based temperature sensors. First, our sensor operates with simple, low-cost one-point calibration. Second, it uses delay-locked loops (DLLs) to convert inverter delays to digital temperature outputs: the use of DLLs enables low energy (0.24 μJ/sample) and high bandwidth (5 kilo-samples/s), facilitating fast thermal monitoring. After calibration, measurement errors for 15 chips fabricated in digital CMOS 0.13 μm fall within -4.0~4.0 °C in a temperature range of 0~100 °C, where the temperature chamber used has a control uncertainty of ±1.1 °C. Microprocessor thermal profiling can be a potential application.

A low power variable length decoder for MPEG-2 based on nonuniform fine-grain table partitioning

Variable length coding is a widely used technique in digital video compression systems. Previous work related to variable length decoders (VLDs) was primarily aimed at high throughput applications, but the increased demand for portable multimedia systems has made power a very important factor. In this paper, a data-driven variable length decoding architecture is presented, which exploits the signal statistics of variable length codes to reduce power. The approach uses fine-grain lookup table (LUT) partitioning to reduce switched capacitance based on codeword frequency. The complete VLD for MPEG-2 has been fabricated and consumes 530 /spl mu/W at 1.35 V with a video rate of 48-M discrete cosine transform samples/s using a 0.6-/spl mu/m CMOS technology. More than an order of magnitude power reduction is demonstrated without performance loss compared to a conventional parallel decoding scheme with a single LUT.

Power scalable processing using distributed arithmetic

A recent trend in low power design has been the employment of reduced precision processing methods for decreasing arithmetic activity and average power dissipation. Such designs can trade off power and arithmetic precision as system requirements change. This work explores the potential of Distributed Arithmetic (DA) computation structures for low power precision-on-demand computation. We present two proof-of-concept VLSI implementations whose power dissipation changes according to the precision of the computation performed.

A high performance SSL IPSEC protocol aware security processor

A 64M transistor security macro processor enables 40k full SSL handshakes per second with 1024 b RSA. The 3DES, AES, ARC4, SHA-1, MD5 and modular exponentiation cryptographic primitives are also supported. The processor is fabricated in a 0.13 /spl mu/m 8M CMOS process and consumes 12 W at 500 MHz.

A low-power IDCT macrocell for MPEG2 MP@ML exploiting data distribution properties for minimal activity

This work describes the implementation of a low power IDCT chip targetted to medium and low bitrate applications. Our strategy for reducing the chip power was two-fold: first, we selected an IDCT algorithm that minimizes activity by exploiting the relative occurence of zero-valued DCT coefficients in compressed video. Previous IDCT implementations have relied on conventional fast IDCT algorithms that perform a constant number of operations per block independent of the data distribution. Our approach performs a variable number of operations that depends on the statistical properties of the input data. Second, we minimized the energy through aggressive voltage scaling using deep pipelining and appropriate circuit techniques so that the chip could produce 14 Msamples/sec (640x480, 30 fps, 4:2:0) at 1.3V in a standard 3.3V process (VTP = -0.9V, VTN=0.7V) and meet the requirement for MPEG2 MP@ML.

A low-power DCT core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization

This work describes the implementation of a DCT (Discrete Cosine Transform) chip targeted to low power video (MPEG2 MP@ML) and still image (JPEG) applications. The chip exhibits two innovative techniques for arithmetic operation reduction in the DCT computation context (MSB rejection and row-column classification) along with standard voltage scaling techniques such as pipelining and parallelism.