Kyoungho Woo

Dual-DLL-based CMOS all-digital temperature sensor for microprocessor thermal monitoring

Todays microprocessors increasingly need on-chip temperature sensors for thermal and power management [1]. Since these sensors do not take part in the main computing activity but rather play the auxiliary, albeit important, role of temperature monitoring, their presence in terms of area, power, and design effort should be minimal, thus, all-digital sensors are desired. Temperature sensing based on temperature-dependent delays of inverters [2] could be suited for microprocessor applications, as it lends itself to digital implementation: by using a time-to-digital converter (TDC), an inverter delay can be compared to an absolute delay reference and converted to a digital temperature output [2] (Fig. 3.7.1). We report on an all-digital CMOS temperature sensor for microprocessor application, which also exploits temperature-dependent inverter delays within the TDC-based framework of Fig. 3.7.1. It, however, has two improvements over prior art of [2]. First, it removes the effect of process variation on inverter delays via calibration at one temperature point (instead of 2-point calibration of [2]), thus, reducing high volume production cost. Second, we use two fine-precision DLLs, one to synthesize a set of temperature-independent delay references in a closed loop, the other as a TDC to compare temperature-dependent inverter delays to the references. The use of DLLs simplifies sensor operation and yields a high measurement bandwidth (5kS/s) at 7b resolution, which could enable fast temperature tracking. This is in contrast to [2], where a counter-based cyclic TDC with an open-loop single delay-reference has a longer measurement time for a similar resolution.

Fast-Lock Hybrid PLL Combining Fractional-

We introduce a single-loop PLL that operates in a narrower-bandwidth, integer-N mode during phase lock and in a wider-bandwidth, fractional-N mode during transient. This hybrid PLL, as a generalization of the conventional variable-bandwidth PLL that shifts only its bandwidth, simultaneously achieves the fast-locking advantage of the fractional-N PLL and design simplicity of the integer-N PLL, and as such, brings benefits in certain important PLL applications. In addition, the frequency division mode switching, unique in the hybrid PLL, enables a new, more digital protocol to execute bandwidth switching. A CMOS IC prototype attests to the validity of the proposed approach.

N

We report on CMOS temperature sensors that work by measuring temperature-dependent delays in CMOS inverters. Two new features distinguish this work from the prior delay-based temperature sensors. First, our sensor operates with simple, low-cost one-point calibration. Second, it uses delay-locked loops (DLLs) to convert inverter delays to digital temperature outputs: the use of DLLs enables low energy (0.24 μJ/sample) and high bandwidth (5 kilo-samples/s), facilitating fast thermal monitoring. After calibration, measurement errors for 15 chips fabricated in digital CMOS 0.13 μm fall within -4.0~4.0 °C in a temperature range of 0~100 °C, where the temperature chamber used has a control uncertainty of ±1.1 °C. Microprocessor thermal profiling can be a potential application.

and Integer-

-The nonlinear transmission line is a structure where short-duration pulses called electrical solitons can be created and propagated. By combining, in a closed-loop topology, the nonlinear line and a special amplifier that provides not only gain but also mechanisms to tame inherently unruly soliton dynamics, we recently constructed the first electrical soliton oscillator that self-generates a stable, periodic train of electrical soliton pulses (Ricketts et al., IEEE Trans. MTT, 2006). This paper starts with a review of this recently introduced circuit concept, and then reports on new contributions, i.e., further experimental studies of the dynamics of the stable soliton oscillator and a CMOS prototype demonstrating the chip-scale operation of the stable soliton oscillator. Finally, we go to the opposite end of the spectrum and present a numerical study showing the possibilities that deliberate promotions of the unruly soliton dynamics in the closed-loop topology can produce chaotic signals.

N

This paper reports a single-loop PLL that operates wide-bandwidth fractional-N mode(without any fractional spur reduction circuits) during transient and in a narrow-bandwidth integer-N mode in locked state. This hybrid operation executed via a simple reconfiguration of the single-loop attains both fast locking and design simplicity, a combination that has been previously difficult to achieve. The frequency division mode switching allows the loop bandwidth switching to be performed in a more digital fashion which increases the degree of design freedom for bandwidth switching. A 2.4GHz CMOS prototype synthesizer with a 1MHz resolution performing the hybrid operation has a 20mus lock time for a 64MHz frequency jump, which is 4 times faster than its fixed integer-N operation.

Modes of Differing Bandwidths

We review three examples (two PLLs [Crowley, 1979; Woo et al.] and one on-chip transmission-line resonator [Andress and Ham, 2005] ) of design tradeoffs which can in fact be circumvented; the key in each case is that the parameters that seem to trade off with each other are actually separated in time or space. This paper is an attempt to present these designs in such a way that this common approach can hopefully be applied to other circuits.

Time-Domain CMOS Temperature Sensors With Dual Delay-Locked Loops for Microprocessor Thermal Monitoring

We review three examples (an on-chip transmission line resonator [1], a phase-locked loop [2], and an analog-to-digital converter [3]) of design tradeoffs which can in fact be circumvented; the key in each case is that the parameters that seem to trade off with each other are actually separated in time or space. This paper is an attempt to present these designs in such a way that this common approach can hopefully be applied to other circuits. We note reader that this paper is not a new contribution, but a review in which we highlight the common theme from our published works [1-3]. We published a similar paper [4], which, however, used only two examples from [1] and [2]. With the newly added content from [3] in the list of our examples, the present paper offers an expanded scope.

On the Self-Generation of Electrical Soliton Pulses

This paper introduces a new frequency synthesizer architecture that operates in a classical (no high-order ¿¿ modulator) fractional-N mode with a wide loop bandwidth in transient and in an integer-N mode with a narrow loop bandwidth in steady state. This unique hybrid operation is executed via simple reconfiguration of frequency dividers and loop filters in the same loop. The hybrid nature of the PLL allows for fast settling and design simplicity simultaneously, and also permits the loop bandwidth switching with the same charge pump current, all of which have been historically a significant hurdle. Behavioral simulations confirm the validity of the proposed approach.