Sean R. Atsatt

Arria™ 10 device architecture

This paper presents the architecture of Arria 10, a high-density FPGA family built on the TSMC 20SOC process. The design of the device includes an embedded dual-core 1.5 GHz ARM A9 subsystem with peripherals, more than 1M logic elements (LEs) and 1.7M user flip-flops, and 64Mb of embedded memory organized into configurable memory blocks. The Arria 10 family is also the first mainstream FPGA family to include hardened single-precision IEEE 754 floating point, with an aggregate throughput of 1.3 TFLOPs. Device I/O consists of 28G programmable transceivers with an enhanced PMA architecture hardened PCIe sub-blocks and hardened DDR external memory controllers. New methods for digitally-assisted analog calibration are used to address process variation. The fabric is optimized for an aggressive die-size reduction and power improvement over 28nm FPGAs and includes features such as time-borrowing FFs for micro-retiming, tri-stated long-lines for improved routability, programmable back-bias at LAB-cluster granularity and power-management features such as Smart-VID for balancing leakage and performance across the process distribution.

Design of a high-density SoC FPGA at 20nm

This article consists of a collection of slides from the authors conference presentation on the special features, system design and architectures, processing capabilities, and targeted markets for Alteras Arria 10 family of processor products.