Herman Henry Schmit

Stratix™ 10 High Performance Routable Clock Networks

We present the clock architecture of the Stratix?10 FPGA, which uses a routable clock network rather than the fixed clock networks of previous generations. We describe the flexibility provided by this routable clock network and how arbitrarily sized clock trees can be synthesized and placed anywhere on the FPGA. We show how this capability to generate customized clock trees can provide better performance through reduced clock loss while maintaining the ability to handle the large number of clock domains that modern systems require. We experimentally demonstrate how a routable clock tree reduces the clock loss of the user design implementation by up to 6% of clock insertion delay.

Packet arrival time in 1588 for 40GE/100GE

1588 timestamping assumes a well-defined instant at which the beginning of a packet crosses the reference plane between the precision time protocol (PTP) node and the network. However, this definition is not clear in the case of a multi-lane serial bus such as 40GE/100GE. Furthermore, there is an implied time-ordering between the lanes of a serial bus that is not captured in the existing definition. This paper explores issues with multi-lane serial buses as it relates to time-stamping and proposes revised definitions for packet arrival time in the case of a serial bus.