Sebastian Turullols

The Oracle Sparc T5 16-Core Processor Scales to Eight Sockets

The Oracle Sparc T5 processor more than doubles the throughput of the Sparc T4 processor, while increasing per-thread performance, scalability, power efficiency, and I/O bandwidth. The authors detail the improvements and new features leading to this latest Oracle Sparc processor.

The next-generation 64b SPARC core in a T4 SoC processor

The T4 microprocessor introduces the next generation dual-issue, out-of-order SPARC core that delivers up to 5x integer and 7x floating-point single-thread performance improvement for both commercial and industry standard work- loads. Eight SPARC cores, a crossbar and a unified 16-way 4MB L3 cache are implemented in the same system-on-chip platform as the predecessor T3 to utilize established coherency (CLC), DDR3 (MCU), PCIE Gen2 (PEU) and 1G/10G Ethernet interfaces (NIL)). Further, T4s pin, thermal and power compatibility with the previous generation enables faster time to market for new multi-socket systems. The 403mm2 die has 855 million transistors of four different types and 12 metal layers fabricated using TSMCs 40nm process.

A 3.6 GHz 16-Core SPARC SoC Processor in 28 nm

The 3.6 GHz SPARC T5 processor is Oracles next generation CMT SoC processor implemented in TSMCs 28 nm process with 1.5 billion transistors. Significant performance improvements were made by doubling the previous generations number of cores to 16 and L3 cache size to 8 MB while increasing bandwidth by nearly 3×. Power efficiency was improved through features like DVFS, core-pair cycle skipping and SerDes power scaling. The SPARC T5 processor has been designed to fit in systems that can scale from 1 to 8 sockets, or 128 to 1024 threads, in glueless fashion. The diverse system-level bandwidth requirements of up to 5.65 TB/sec in these systems are met by advanced SERDES design that handles up to 30 dB loss in an area and power efficient manner. The different thermal envelopes of these systems are addressed by power management features that span software, system and chip design.

4.3 Fine-grained adaptive power management of the SPARC M7 processor

The power management system described in this paper enables more than 3× increase in power-constrained performance over the previous generation of SPARC server CPUs [2]. The low latency and high performance of the system is possible due to accurate, high-bandwidth sensors, fast on-die control and finegrained actuation implemented using both clock cycle skipping and DVFS, as required by the time constants of system constraints.

Asymmetric Frequency Locked Loop (AFLL) for adaptive clock generation in a 28nm SPARC M6 processor

In order to minimize the impact of on-chip Ldi/dt noise on power and performance, Oracles SPARC M6 processor features an Asymmetric Frequency Locked Loop (AFLL) that dynamically adjusts chip frequency. It achieves 15% improved noise immunity by reacting to the voltage noise asymmetrically through the use of a pair of DCOs that accurately track the response of critical paths. The AFLL is implemented in 28nm CMOS process in 0.045mm2 of area, dissipating 14mW, and reducing jitter by 50%.

Bandwidth and power management of glueless 8-socket SPARC T5 system

Continuous advancement in multicore and multi-threaded design requires optimized integration of hardware and software to address increasing bandwidth and power management challenges for high-end system designs. The next generation Oracle T-series systems utilizing the SPARC T5 processor address these challenges. These systems scale from one to eight sockets using a 1-hop glueless connection. The processor implements 16 8-threaded cores, an 8MB L3 cache, four on-chip memory controllers and two on-chip PCIE Gen 3 interfaces [1]. The 8-socket system comprises an unprecedented 1024 threads to deliver the highest thread count ever in any T-series system. The fully configured 8-socket T5 system supports DDR3-1066-based memory bandwidth, which reaches over 2.9TB/s, coherence bandwidth of 2+TB/s and PCI Gen 3 bandwidth with 256GB/s to deliver 5+TB/s throughput (Fig. 3.7.1).

SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor

The SPARC M7 processor offers up to 3 × the throughput performance of Oracles previous SPARC processor generation for many enterprise workloads. It contains 32 highly optimized S4 cores that include a more efficient L2 cache scheme, support for VIS extensions, virtual address masking, and user-level synchronization instructions to provide substantial single thread performance over the predecessor design. A total of 256 threads per chip provide the throughput performance required by even the most demanding enterprise applications. Both throughput and single thread performance benefit from a large fully shared 64 MB on-chip L3 cache with very low latency. The 0.5 TB/s on-chip communications bandwidth requirements are served via a semi-custom on-chip network (OCN) in place of the traditional crossbar. Hardware database analytics accelerator units (DAX) achieve up to 10 × the performance for in-memory database queries, include decompression and messaging operations, and support pointer version checking for securing application data through application data integrity (ADI), as well as fine grained memory migration. The SerDes IO operate up to 18 Gbps, offering 1 TB/s total bandwidth for memory and multi-socket interfaces. New on-chip power management features include fast and accurate dynamic power meters, thermal sensors, and a fine-grain thermal, current, and chip power control engine to enable maximum performance/Watt. Special circuits like the voltage shift module (VSM) were developed to cope with the clock and voltage domain crossing issues, while the asymmetric frequency lock loop (AFLL) main clock generation circuit also provides Ldi/dt droop compensation leading to substantial power savings.

SPARC T5: 16-core CMT processor with glueless 1-hop scaling to 8-sockets

This article consists of a collection of slides from the authors conference presentation on Oracles SPARC T5, a 16-core CMT processor with glueless 1-Hop scaling to 8-sockets. The powerpoint display is intended to outline the companys general product direction. It is intended for information purposes only, and may not be incorporated into any contract. It is not a commitment to deliver any material, code, or functionality, and should not be relied upon in making purchasing decisions. The development, release, and timing of any features or functionality described for Oracle’s products remains at the sole discretion of Oracle.

A 28nm 3.6GHz 128 thread SPARC T5 processor and system applications

The SPARC T5 processor implements 16 8-threaded SPARC S3 cores, an 8-MB 16-way set-associative L3 cache, 8 BL8 DDR3-1066 schedulers, and integrated PCIe Gen-3. The processor doubles the performance of the previous generation SPARC T4 CPU and expands support for up to 8 socket systems in a single hop glueless fashion. It is implemented in the TSMC 28nm process using 1.5 billion transistors and a 13 layer metal stack. The chip has a maximum operating frequency of 3.6 GHz.