Sebastiano Strangio

Mixed Tunnel-FET/MOSFET Level Shifters: A New Proposal to Extend the Tunnel-FET Application Domain

In this paper, we identify the level shifter (LS) for voltage up-conversion from the ultralow-voltage regime as a key application domain of tunnel FETs (TFETs). We propose a mixed TFET-MOSFET LS design methodology, which exploits the complementary characteristics of TFET and MOSFET devices. Simulation results show that the hybrid LS exhibits superior dynamic performance at the same static power consumption compared with the conventional MOSFET and pure TFET solutions. The advantage of the mixed design with respect to the conventional MOSFET approach is emphasized when lower voltage signals have to be up-converted, reaching an improvement of the energy-delay product up to three decades. When compared with the full MOSFET design, the mixed TFET-MOSFET solution appears to be less sensitive toward threshold voltage variations in terms of dynamic figures of merit, at the expense of higher leakage variability. Similar results are obtained for four different LS topologies, thus indicating that the hybrid TFET-MOSFET approach offers intrinsic advantages in the design of LS for voltage up-conversion from the ultralow-voltage regime compared with the conventional MOSFET and pure TFET solutions.

Impact of TFET Unidirectionality and Ambipolarity on the Performance of 6T SRAM Cells

We use mixed device-circuit simulations to predict the performance of 6T static RAM (SRAM) cells implemented with tunnel-FETs (TFETs). Idealized template devices are used to assess the impact of device unidirectionality, which is inherent to TFETs and identify the most promising configuration for the access transistors. The same template devices are used to investigate the VDD range, where TFETs may be advantageous compared to conventional CMOS. The impact of device ambipolarity on SRAM operation is also analyzed. Realistic device templates extracted from experimental data of fabricated state-of-the-art silicon pTFET are then used to estimate the performance gap between the simulation of idealized TFETs and the best experimental implementations.

Assessment of InAs/AlGaSb Tunnel-FET Virtual Technology Platform for Low-Power Digital Circuits

In this work, a complementary InAs/Al0.05Ga0.95Sb tunnel field-effect-transistor (TFET) virtual technology platform is benchmarked against the projection to the CMOS FinFET 10-nm node, by means of device and basic circuit simulations. The comparison is performed in the ultralow voltage regime (below 500 mV), where the proposed III-V TFETs feature ON-current levels comparable to scaled FinFETs, for the same low-operating-power OFF-current. Due to the asymmetrical n- and p-type I-Vs, trends of noise margins and performances are investigated for different Wp/Wn ratios. Implications of the device threshold voltage variability, which turned out to be dramatic for steep slope TFETs, are also addressed.

An Ultralow-Voltage Energy-Efficient Level Shifter

This brief presents an energy-efficient level shifter (LS) able to convert extremely low level input voltages to the nominal voltage domain. To obtain low static power consumption, the proposed architecture is based on the single-stage differential-cascode-voltage-switch scheme. Moreover, it exploits self-adapting pull-up networks to increase the switching speed and to reduce the dynamic energy consumption, while a split input inverting buffer is used as the output stage to further improve energy efficiency. When implemented in a commercial 180-nm CMOS process, the proposed design can up-convert from the deep subthreshold regime (sub-100 mV) to the nominal supply voltage (1.8 V). For the target voltage level conversion from 0.4 to 1.8 V, our LS exhibits an average propagation delay of 31.7 ns, an average static power of less than 60 pW, and an energy per transition of 173 fJ, as experimentally measured across the test chips.

Low Frequency Noise and Gate Bias Instability in Normally OFF AlGaN/GaN HEMTs

In this brief, traps-related dispersion phenomena are investigated on GaN/AlGaN MOS-high-electron mobility transistors. Pulsed I-V characteristics and low-frequency-noise measurements are the characterization vehicles used to get a direct insight of the device trap-states. By considering a set of ten samples, device-to-device fluctuation parameters extracted from trap-related measurements (1/f noise and gate bias instability) are systematically compared with conventional electrical parameters (threshold voltage and ON-current). Two separate trends are identified and ascribed to two different trap families.

Benchmarks of a III–V TFET technology platform against the 10-nm CMOS technology node considering 28T Full-Adders

This paper presents a benchmark of a virtual III-V TFET nanowire technology platform against the predictive models of CMOS FinFETs for the 10-nm technology node. The standard 28T full adder and the 32-bits ripple carry adder are used as vehicle circuit/architecture for the comparison, respectively. Figures-of-merit including delays, energy and energy-delay plots are discussed.

Analysis of TFET based 6T SRAM cells implemented with state of the art silicon nanowires

Tunnel-FETs are studied in a mixed device/circuit simulation environment. Model parameters calibrated on experimental DC as well as pulsed characterizations are then used for 6T SRAM cells investigation. Issues concerning fabricated devices, as the ambipolarity and the uni-directionality, are addressed at both device and circuit levels. Our results suggest that ambipolarity needs to be solved through device engineering and/or fabrication process improvements, while issues related to uni-directionality may be mitigated with a proper circuit design.

Understanding the Potential and Limitations of Tunnel FETs for Low-Voltage Analog/Mixed-Signal Circuits

In this paper, the analog/mixed-signal performance is evaluated at device and circuit levels for a III-V nanowire tunnel field effect transistor (TFET) technology platform and compared against the predictive model for FinFETs at the 10-nm technology node. The advantages and limits of TFETs over their FinFET counterparts are discussed in detail, considering the main analog figures of merits, as well as the implementation of low-voltage track-and-hold (T/H) and comparator circuits. It is found that the higher output resistance offered by TFET-based designs allows achieving significantly higher intrinsic voltage gain and higher maximum-oscillation frequency at low current levels. TFET-based T/H circuits have better accuracy and better hold performance by using the dummy switch solution for the mitigation of the charge injection. Among the comparator circuits, the TFET-based conventional dynamic architecture exhibits the best performance while keeping lower area occupation with respect to the more complex double-tail circuits. Moreover, it outperforms all the FinFET counterparts over a wide range of supply voltage when considering low values of the common-mode voltage.

Single Defect Discharge Events in Vertical-Nanowire Tunnel-FETs

In this paper, we investigate the single defect discharge events in Ge-source n-type vertical nanowire tunnel field effect transistors, by monitoring the relaxation phase which follows bias temperature instability (BTI) stress. Threshold voltage shift induced by single discharge events follows a bimodal Weibull distribution, with the location parameter of the second mode being significantly higher than the first one. Both modes are temperature independent. Based on TCAD simulations, we propose that the second mode is associated with defects located at the source/channel junction close to the channel/oxide interface, while the first mode is ascribed to oxide traps far from the source/channel junction. Although present in smaller numbers, such traps with a larger average impact on the device characteristics are expected to dominate the BTI-induced variability in a large population of nanoscale devices for realistic applications.

Performance analysis of different SRAM cell topologies employing tunnel-FETs

Tunnel-FET is one of the most promising candidates to replace CMOS in low-power (LP) applications [1], featuring a sub-threshold slope (SS) below the 60mV/dec limit of MOSFET. However, the intrinsic asymmetry of TFETs, makes them good transistors only for a current flowing from drain to source and prevents their use as access transistors (AT) in the 6T SRAM cell. In this paper, we use TCAD mixed device-circuit simulations [2] of symmetric 6T SRAM cells, implemented with the n-type SiGe/Si TFET and p-type strained-Si TFET designed in [3] (Fig. 1) for VDD as low as 0.2V. The gate metal work-functions were set to match the off-current for LP applications (10pA/μm). For comparison purposes, both N- and P-MOS were also designed with the same double-gate SOI structure. The ID-VGS curves of the TFETs (Fig.2) show that the sub-60mV/decade region is confined to ultra low voltage regime (below 0.25 V) and that ambipolarity is very limited in these devices. ID(VDS) in Fig.3 show the lower output conductance of the TFETs w.r.t. to MOS.