Yong-Cheol Bae

An overview of KSTAR results

Since the first H-mode discharges in 2010, the duration of the H-mode state has been extended and a significantly wider operational window of plasma parameters has been attained. Using a second neutral beam (NB) source and improved tuning of equilibrium configuration with real-time plasma control, a stored energy of Wtot???450?kJ has been achieved with a corresponding energy confinement time of ?E???163?ms. Recent discharges, produced in the fall of 2012, have reached plasma ?N up to 2.9 and surpassed the n?=?1 ideal no-wall stability limit computed for H-mode pressure profiles, which is one of the key threshold parameters defining advanced tokamak operation. Typical H-mode discharges were operated with a plasma current of 600?kA at a toroidal magnetic field BT?=?2?T. L?H transitions were obtained with 0.8?3.0?MW of NB injection power in both single- and double-null configurations, with H-mode durations up to ?15?s at 600?kA of plasma current. The measured power threshold as a function of line-averaged density showed a roll-over with a minimum value of ?0.8?MW at . Several edge-localized mode (ELM) control techniques during H-mode were examined with successful results including resonant magnetic perturbation, supersonic molecular beam injection (SMBI), vertical jogging and electron cyclotron current drive injection into the pedestal region. We observed various ELM responses, i.e. suppression or mitigation, depending on the relative phase of in-vessel control coil currents. In particular, with the 90? phase of the n?=?1 RMP as the most resonant configuration, a complete suppression of type-I ELMs was demonstrated. In addition, fast vertical jogging of the plasma column was also observed to be effective in ELM pace-making. SMBI-mitigated ELMs, a state of mitigated ELMs, were sustained for a few tens of ELM periods. A simple cellular automata (?sand-pile?) model predicted that shallow deposition near the pedestal foot induced small-sized high-frequency ELMs, leading to the mitigation of large ELMs. In addition to the ELM control experiments, various physics topics were explored focusing on ITER-relevant physics issues such as the alteration of toroidal rotation caused by both electron cyclotron resonance heating (ECRH) and externally applied 3D fields, and the observed rotation drop by ECRH in NB-heated plasmas was investigated in terms of either a reversal of the turbulence-driven residual stress due to the transition of ion temperature gradient to trapped electron mode turbulence or neoclassical toroidal viscosity (NTV) torque by the internal kink mode. The suppression of runaway electrons using massive gas injection of deuterium showed that runaway electrons were avoided only below 3?T in KSTAR. Operation in 2013 is expected to routinely exceed the n?=?1 ideal MHD no-wall stability boundary in the long-pulse H-mode (?10?s) by applying real-time shaping control, enabling n?=?1 resistive wall mode active control studies. In addition, intensive works for ELM mitigation, ELM dynamics, toroidal rotation changes by both ECRH and NTV variations, have begun in the present campaign, and will be investigated in more detail with profile measurements of different physical quantities by techniques such as electron cyclotron emission imaging, charge exchange spectroscopy, Thomson scattering and beam emission spectroscopy diagnostics.

A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme

Mobile DRAM is widely adopted in battery-powered portable devices because of its low power. Recently, in mobile devices such as smart phones and tablet PCs, higher performance is required to support 3D gaming mode and high-quality video. These trends lead to consideration of higher-performance DRAMs than LPDDR2, while the power budget for DRAMs for mobile devices cannot increase. DRAMs with wide I/O or serial I/O have been reviewed as candidates for over 6.4GB/s channel bandwidth. However, wide-I/O DRAMs [1] must solve issues such as stacking yield for higher density and failure analysis modeling of system-in-package (SiP), and most serial I/Os have worse I/O power efficiency than LPDDR2. For an evolutionary successor of LPDDR2, therefore, we design a 1.2V 1.6Gb/s/pin ×32 4Gb low-power DDR3 SDRAM (LPDDR3) with input skew calibration and enhanced refresh control schemes, achieving 6.4GB/s total data bandwidth. Most features of LPDDR3 are backward compatible with LPDDR2, except that channel termination, command-address (CA) training, and write leveling are adopted.

A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation

A 1.0 V 8 Gbit LPDDR4 SDRAM with 3.2 Gbps/pin speed and integrated ECC engine for sub-1 V DRAM core is presented. DRAM internal read-modify-write operation for data masked write makes the integrated ECC engine possible in a commodity DRAM. Time interleaved latency and IO control circuits enable 1.0 V operation at target speed. To reach 3.2 Gbps with improved power efficiency over conventional mobile DRAMs, the following IO features are introduced: Low voltage swing terminated logic drivers with VOH level calibration and periodic ZQ calibration, unmatched DQ/DQS scheme and DQS oscillator for DQS tree delay tracking. This chip is fabricated in 25 nm DRAM process on 88.1 mm 2 die area.

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme

With growing demand for low-power mobile applications, such as wearable devices, smart phones and tablet PCs, low-power mobile DRAM has been identified as a mandatory requirement for low-power system designs. The recently developed LPDDR4 [1] is still a power efficient solution because of its architectural approaches and low-voltage-swing terminated logic (LVSTL). However, demand for enhanced power-efficiency beyond LPDDR4 is still increasing for mobile applications. In this work, a 5.0Gbp/s/pin 8Gb LPDDR4X memory with power-isolated low-voltage-swing terminated logic (PI-LVSTL) and a split-die architecture is proposed to enhance power-efficiency and mass production yield.

A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution

Demand for higher bandwidth DRAM continues to increase, especially in high-performance computing and graphics applications. However, conventional DRAM devices such as DDR4 DIMM and GDDR5 cannot satisfy these needs since they are bandwidth limited to less than 30GB/s. Also, if multiple GDDR DRAMs are used simultaneously for higher bandwidth, then high power consumption and routing congestion on PCBs become a big concern. In order to overcome these limitations, the high-bandwidth memory (HBM) DRAM was recently introduced[1]. HBM-DRAM uses TSV and interposer technologies enabling multiple chip stacks and wide I/Os between the processor and memory: providing high capacity, low power and high bandwidth. This paper proposes the 2nd generation HBM to double the bandwidth from 128GB/s to more than 256GB/s and support pseudo-channel mode and 8H stacks [2]. In the pseudo-channel mode, a legacy channel is divided into two pseudo channels and the two pseudo channels share the command-address pins. Thus, one HBM has 16 pseudo channels instead of 8 legacy channels. To support various stack configurations including 8H stacks, a new architecture is adopted for flexible density ranging from 16Gb to 64Gb maintaining the same bandwidth. Finally, the bandwidth increase requires an active thermal solution to manage hotspots that develop from highly concentrated power consumption; we propose an adaptive refresh considering temperature distribution (ART) scheme as a solution.

A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface

A 6.4Gb/s TX-interleaving (TI) technique at sub-1V supply voltage is implemented with 25nm DRAM process for the future mobile DRAM interface which requires 51.2 GBps (2X Bandwidth of LPDDR4). A newly proposed 2-channel TX interleaving technique with a bootstrapping switch can save power consumption drastically by eliminating repeaters, while operating at 6.4 Gb/s with 40 % enhancement of I/O power efficiency compared to that of the LPDDR4.