Seiji Imai

Undoped epitaxial Si channel n-MOSFET grown by UHV-CVD with preheating

Undoped epitaxial channel n-MOSFET with high transconductance was developed. In order to obtain a good crystal quality of the epitaxial layer and, thus, to achieve high performance, it is important to reduce the oxygen concentration at the epitaxial Si/Si substrate interface. In this paper, we describe the relationship between the electrical characteristics and the surface density of oxygen at the epitaxial Si/Si substrate. We also describe the dependence of the electrical characteristics on epitaxial Si thickness. The g/sub m/ of n-MOSFET with 40-nm epitaxial Si for 0.10-/spl mu/m gate length was 630 mS/mm at V/sub d/-1.5 V, and the drain current was 0.77 mA//spl mu/m. This g/sub m/ value in the case of the epitaxial Si channel is about 20% larger than that of bulk the MOSFET. These results show that epitaxial Si channel MOSFETs are useful for future high-speed ULSI devices.

Measurement of Hall Mobility in 4H-SiC for Improvement of the Accuracy of the Mobility Model in Device Simulation

In order to construct a reliable parameter set for the physic al modeling of 4H-SiC, we are collecting and examining the physical parameters. The results of mobility measurement are presented and compared with the built-in model in the device simulator. The doping depe n nce of the electron mobility is in agreement with the built-in model, whereas that of the hole mobility is different from the built-in model in the higher doping region. Further, the anisotropy of the electron and hole mobility is investigated. The anisotropy of the electron mobility ) 0001 ( / ) 00 1 1 ( > < μ > < μ is about 0.83 and is in agreement with the built-in model. The anisotropy of the hole mobility is observed and it is estimated to be 1.15. To our knowledge, this is the first report of the anisotropy of the hole mobility in 4H-SiC. Introduction Silicon carbide devices have outstanding features, namely higher speed and lower loss than silicon devices. Among the many polytypes of SiC, 4H-SiC has attracted gre at att ntion as a candidate material for the next generation of power semiconductor devices, due t o the excellent physical properties such as the electric breakdown field and mobility. In order to r alize SiC devices that make the best use of the excellent physical properties, device simulati on technology of SiC is indispensable. However, the comprehensive and reliable parameter set for the physic al modeling of 4H-SiC for device simulators has not been reported. As a first step in the construction of a reliabl e par meter set for the physical modeling of 4H-SiC, we are collecting and examini ng the physical parameters systematically by fabricating test chips that consist of the el ments for physical property measurements. This paper is the first report on our ongoing research . The final goal of our research is the release of the comprehensive parameter set. In this paper, we present results of mobility measurement and compare them with the previous results. Experimental Figure 1 shows the top view of a test chip of the first lot. A prec ise patterning of contact, electrode and mesa by the mask process guarantees the precision of the physical property measurements. A test chip consists of elements (Hall bars and the square and clover shaped four terminal pattern) for mobility measurements and pin diodes for the impact ionization coefficient mea surements. Hall bars are tilted to the crystallographic axis every fifteenth degree in order to de ect the anisotropy of the mobility. Test chips were fabricated on 4H-SiC epitaxial wafers. For the measurements of the electron mobility, Materials Science Forum Online: 2003-09-15 ISSN: 1662-9752, Vols. 433-436, pp 443-446 doi:10.4028/www.scientific.net/MSF.433-436.443

Optimum Design of a SiC Schottky Barrier Diode Considering Reverse Leakage Current due to a Tunneling Process

The optimization of the Schottky barrier height (SBH) and the maximum electric fields at the interface of a 4H-SiC Schottky barrier diode (SBD) is discussed, considering the reverse leakage current due to tunneling process. We first show that the reverse characteristics of a Ti/4H-SiC SBD are well described by the tunneling theory. Based on the tunneling theory, we show that the maximum electric field decreases as the Schottky barrier height decreases, and becomes smaller than the avalanche breakdown field of SiC. The on-state voltage as a function of the SBH is calculated, considering the specification of a leakage current. The calculated results show that the optimum SBH for a 4H-SiC SBD of 600V class is 0.9eV and that of 2000V class is 1.2eV. Introduction An SBD on 4H-SiC has outstanding features, namely higher speed and lower loss than a conventional SBD on silicon. A SiC SBD is designed so that the electric field at the Schottky interface is about ten times as large as that of a Si SBD, when the reverse bias is applied, because the breakdown electric field of SiC is about ten times as large as that of Si. This design principle of a SiC SBD is the origin of the high performance. However, the high electric fields at the Schottky interface of a SiC SBD bring about the increase of the reverse leakage current. In fact, the measured reverse leakage current of a SiC SBD is much higher than the reverse leakage current calculated by the classical Schottky theory. Thus, the effects of high electric fields at the Schottky interface on the reverse leakage current of SBDs have attracted much attention. Crofton and Sriram pointed out that the reverse leakage current of a SiC SBD is mainly due to tunneling process induced by the high electric field at the Schottky interface [1]. Treu and his co-workers investigated the reverse characteristics of 4H-SiC SBDs, and concluded that they are described by the thermionic field emission model [2], which is the approximation of tunneling current derived by Padvani and Stratton [3]. The present authors identified dominant mechanisms of the reverse leakage current as a function of the electric field and the SBH. We derived the compact and closed analytical expression of the reverse leakage current of a SiC SBD [4]. As the reverse leakage current due to tunneling process depends mainly on the SBH and the electric fields at the interface, it is important to optimize the SBH and the maximum electric fields at the interface for the design of a SiC SBD. In this work, we first present the reverse characteristics of Ti/4H-SiC SBDs and show that they are well described by the tunneling theory. Then we discuss the optimization the SBH and the maximum electric fields at the interface, considering the reverse leakage current due to tunneling process. Materials Science Forum Online: 2003-09-15 ISSN: 1662-9752, Vols. 433-436, pp 831-834 doi:10.4028/www.scientific.net/MSF.433-436.831

Impact Ionization Coefficients of 4H-SiC

The electric field dependence and anisotropy of the impact ionization coefficients of 4H-SiC are investigated by means of the avalanche breakdown behavior of p + n diodes. The breakdown voltages as a function of doping density and the multiplication factors of a leakage current are obtained using p + n diode fabricated on ) 0001 ( and ) 0 2 11 ( 4H-SiC epitaxial wafers. The obtained impact ionization coefficients show large anisotropy; the breakdown voltage of a p + n diode on ) 0 2 11 ( wafer is 60% of that on ) 0001 ( wafer. We have shown that the anisotropy of the impact ionization coefficients is attributable to the anisotropy of saturation velocity originated from the electronic structure of 4H-SiC. Introduction The impact ionization coefficients are indispensable for predicting the breakdown voltages of power devices by device simulations. However, the reports of measurements of the impact ionization coefficient of 4H-SiC are limited, and they are not in agreement with one another [1,2]. Further, anisotropy of breakdown field of 4H-SiC was reported and it was shown that there is a significant reduction of the breakdown field when the electric field is applied perpendicular to the c-direction [3]. In order to understand avalanche breakdown behavior of a 4H-SiC power device, reliable parameter sets for the impact ionization coefficients are needed. In this paper, we present the parameter sets of impact ionization coefficients of 4H-SiC for 0001 and 0 2 11 directions that reproduce avalanche breakdown behavior of p + n diodes on ) 0001 ( and ) 0 2 11 ( epitaxial 4H-SiC wafers. We also discuss the origin of anisotropy of impact ionization coefficient of 4H-SiC based on the microscopic image of the impact ionization and the transport physics under high electric field. Experimental The breakdown voltages as a function of doping density and the multiplication factors of a leakage current are obtained using p + n diode fabricated on ) 0001 ( and ) 0 2 11 ( 4H-SiC epitaxial wafers. Figure 1 shows a cross section of the p + n diode and the measuring system for multiplication factors. The p + n junction of a diode is located between a p + -type epitaxial layer on p + -type substrate and an n-type epitaxial layer. The doping concentration of the n-type epitaxial layer was between 16 10 3× cm -3 and 17 10 2× cm -3 . Deep mesa for the isolation and the termination of pin diodes was formed using inductively coupled plasma (ICP) reactive ion etching in SF6 chemistries. Nickel was deposited for the contact area after the contact implantation and 1600C activation annealing, and sintered before the Materials Science Forum Online: 2004-06-15 ISSN: 1662-9752, Vols. 457-460, pp 673-676 doi:10.4028/www.scientific.net/MSF.457-460.673

Mobility modulation of two-dimensional hole gas in a p-type Si/SiGe modulation doped heterostructure by back-gating

The mobility limiting mechanism of a two-dimensional hole gas in a strained /Si modulation doped heterostructure was investigated at 4.2 K by means of a back-gating measurement of the mobility. It was shown that the mobility decreased with increasing positive back-gate voltage at a fixed hole density. A self-consistent calculation of the wavefunction indicated that the wavefunction was pushed toward the hetero-interface when a more positive back-gate bias was applied. A comparison between the observed and the calculated mobility modulation due to the wavefunction deformation revealed that the Coulomb scattering by the ionized impurities in the spacer and/or at the hetero-interface limits the mobility.

0.15-/spl mu/m buried-channel p-MOSFETs with ultrathin boron-doped epitaxial Si layer

We demonstrated silicon MOSFETs with a counter-doped ultrathin epitaxial channel grown by low-temperature UHV-CVD; this allows the channel region to be doped with boron with high precision. The boron concentration and epitaxial layer thickness can be chosen independently, and so it is easy to adjust the threshold voltage of the buried-channel p-MOSFETs with n-type polysilicon gates. It was confirmed that choosing an ultrathin epitaxial layer at 10 nm leads to suppression of the short-channel effects in buried-channel p-MOSFETs with gate length down to 0.15 /spl mu/m, while maintaining an appropriate value of threshold voltage.

A 600V Deep-Implanted Gate Vertical JFET

A 4H-SiC 600V class Deep-Implanted gate Vertical JFET (DI-VJFET) is reported. To achieve lower on-resistance and higher blocking-voltage, the design of channel region plays an essential role. Therefore, the channel dimensions were optimized with the ISE device simulator and calculated results were compared with experimental results. Moreover, the actual channel dimensions of fabricated samples were analyzed by SSRM (Scanning Spread Resistance Microscopy) measurements. The potential distributions in on/off-state were analyzed by SPoM (Scanning Potential Microscopy) measurements. The active areas of 2.2x10 -3 , 1.6x10 -2 [cm 2 ] (small chip), and 5.3x10 -2 [cm 2 ] (large chip) were fabricated, in this study. The small chips were evaluated to ascertain the dependence of the electric characteristics on the design parameters. The blocking-voltages were varied up to 1100V, and the on-resistances were varied down to 7.8mΩcm 2 depending on the fabricated channel opening. The DI-VJFET in this work has almost the same electric characteristics as Si Cool-MOSFET. The large chips exhibited specific on-resistance of 16mΩcm 2 , drain current of 5A, and blocking-voltage of 900V. The turn-off speed of the large chip was measured with resistive load circuit. The turn-off time was 200ns for external resistance of 60Ω.

Electrical Characteristics Temperature Dependence of 600V-Class Deep Implanted Gate Vertical JFET

A 4H-SiC 600 V class Deep-Implanted gate Vertical JFET (DI-VJFET) is examined. The DI-VJFET exhibited a specific on-resistance of 13 mΩcm2, drain current of 5 A, and a blocking-voltage of 600 V. In this paper, the very high temperature dependence (R.T.~ 400 oC) of the I-V characteristics is measured and the dominant factor of the on-resistance and the blocking-voltage is discussed. Moreover, the switching waveform of SiC DI-VJFET with SiC SBD is measured by using a half bridge, double-pulse circuit with inductive load at R.T. and 200 oC. The turn-off time is 300 ns at an inductance of 4 mH and an external gate resistance of 100 Ω.