Naoharu Sugiyama

Fabrication of strained Si on an ultrathin SiGe-on-insulator virtual substrate with a high-Ge fraction

A promising fabrication method for a Si1−xGex-on-insulator (SGOI) virtual substrate and evaluation of strain in the Si layer on this SGOI substrate are presented. A 9-nm-thick SGOI layer with x=0.56 was formed by dry oxidation after epitaxial growth of Si0.92Ge0.08 on a silicon-on-insulator substrate. During the oxidation, Ge atoms were rejected from the surface oxide layer and condensed in the remaining SGOI layer, which was partially relaxed without introducing a significant amount of dislocations. It is found from the analysis of the Raman spectra that the strained Si layer grown on the SGOI layer involves a tensile strain of 1%. This strained Si on the SGOI structure is applicable to sub-100-nm metal–oxide–semiconductor field-effect transistors.

Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance

An effective way to reduce supply voltage and resulting power consumption without losing the circuit performance of CMOS is to use CMOS structures using high carrier mobility/velocity. In this paper, our recent approaches in realizing these carrier-transport-enhanced CMOS will be reviewed. First, the basic concept on the choice of channels for increasing on current of MOSFETs, the effective-mass engineering, is introduced from the viewpoint of both carrier velocity and surface carrier concentration under a given gate voltage. Based on this understanding, critical issues, fabrication techniques, and the device performance of MOSFETs using three types of channel materials, Si (SiGe) with uniaxial strain, Ge-on-insulator (GOI), and III-V semiconductors, are presented. As for the strained devices, the importance of uniaxial strain, as well as the combination with multigate structures, is addressed. A novel subband engineering for electrons on (110) surfaces is also introduced. As for GOI MOSFETs, the versatility of the Ge condensation technique for fabricating a variety of Ge-based devices is emphasized. In addition, as for III-V semiconductor MOSFETs, advantages and disadvantages on low effective mass are examined through simple theoretical calculations.

Electron and hole mobility enhancement in strained-Si MOSFET's on SiGe-on-insulator substrates fabricated by SIMOX technology

We have newly developed strained-Si MOSFETs on a SiGe-on-insulator (strained-SOI) structure fabricated by separation-by-implanted-oxygen (SIMOX) technology. Their electron and hole mobility characteristics have been experimentally studied and compared to those of control SOI MOSFETs. Using an epitaxial regrowth technique of a strained-Si film on a relaxed-Si/sub 0.9/Ge/sub 0.1/ layer and the conventional SIMOX process, strained-Si (20 nm thickness) layer on fully relaxed-SiGe (340 nm thickness)-on-buried oxide (100 nm thickness) was formed, and n-and p-channel strained-Si MOSFETs were successfully fabricated. For the first time, the good FET characteristics were obtained in both n-and p-strained-SOI devices. It was found that both electron and hole mobilities in strained-SOI MOSFETs were enhanced, compared to those of control SOI MOSFETs and the universal mobility in Si inversion layer.

Characterization of 7-nm-thick strained Ge-on-insulator layer fabricated by Ge-condensation technique

A strained Ge-on-insulator (GOI) structure with a 7-nm-thick Ge layer was fabricated for applications to high-speed transistors. The GOI layer was formed by thermal oxidation of a strained SiGe layer grown epitaxially on a silicon-on-insulator (SOI) wafer. In transmission electron microscopy measurements, the obtained GOI layer exhibited a single-crystal structure with the identical orientation to an original SOI substrate and a smooth Ge/SiO2 interface. The rms of the surface roughness of the GOI layer was evaluated to be 0.4 nm by atomic force microscopy. The residual Si fraction in the GOI layer was estimated to be lower than the detection limit of Raman spectroscopy of 0.5% and also than the electron energy loss spectroscope measurements of 3%. It was found that the obtained GOI layer was compressively strained with a strain of 1.1%, which was estimated by the Raman spectroscopy. Judging from the observed crystal quality and the strain value, this technique is promising for fabrication of high-mobilit...

A Novel Fabrication Technique of Ultrathin and Relaxed SiGe Buffer Layers with High Ge Fraction for Sub-100 nm Strained Silicon-on-Insulator MOSFETs

A novel fabrication technique for relaxed and thin SiGe layers on buried oxide (BOX) layers, i.e., SiGe on insulator (SGOI), with a high Ge fraction is proposed and demonstrated for application to strained-Si metal-oxide-semiconductor field effect transistors (MOSFETs). This fabrication technique is based on the high-temperature oxidation of the SGOI layers with a lower Ge fraction. It is found that Ge atoms are rejected from the oxide and condensed in the SGOI layers. The conservation of the total amount of Ge atoms in the SGOI layer is confirmed by structural and compositional analyses of dry-oxidized SGOI layers at 1050°C of different initial thicknesses and oxidation times. Using this technique, a 16-nm-thick SGOI layer with the Ge fraction as high as 0.57 is successfully obtained. The Ge profiles across the SGOI layers are quite uniform and the layers are almost completely relaxed. Significant dislocation generation in the SGOI layer is not observed after the oxidation. This is a promising technique for application to sub-100 nm fully-depleted silicon-on-insulator (SOI) MOSFETs with strained-Si or SiGe channels.

Non-volatile Si quantum memory with self-aligned doubly-stacked dots

We propose a novel Si dot memory whose floating gate consists of self-aligned doubly stacked Si dots. A lower Si dot exists immediately below an upper dot and lies between thin tunnel oxides. It is experimentally shown that charge retention is improved compared to the usual single-layer Si dot memory. A theoretical model considering quantum confinement and Coulomb blockade in the lower Si dot explains the experimental results consistently, and shows that charge retention is improved exponentially by lower dot size scaling. It is shown that the retention improvement by lower dot scaling is possible, keeping the same write/erase speed as single dot memory, when the tunnel oxide thickness is adjusted simultaneously.

High mobility Ge-on-insulator p-channel MOSFETs using Pt germanide Schottky source/drain

We demonstrate, for the first time, successful operation of Schottky-barrier source/drain (S/D) germanium-on-insulator (GOI) MOSFETs, where a buried oxide and a silicon substrate are used as a gate dielectric and a bottom gate electrode, respectively. Excellent performance of p-type MOSFETs using Pt germanide S/D is presented in the accumulation mode. The hole mobility enhancement of 50%/spl sim/40% against the universal hole mobility of Si MOSFETs is obtained for the accumulated GOI channel with the SiO/sub 2/-Ge interface.

High-performance strained Si-on-insulator MOSFETs by novel fabrication processes utilizing Ge-condensation technique

Strained SOI (SSOI)-nMOSFETs with enhanced mobility up to 67% were fabricated on a strain-relaxed SiGe-on-insulator substrate using a novel Ge-condensation technique. This method, using only standard Si processes, realizes smooth SSOI surfaces without using SIMOX, wafer bonding, surface polishing or any other special processes. Relaxation ratio of the SiGe substrate was varied from 0% to 100%, resulting in the control of threshold voltage. The Ge-condensation process using conventional SOI substrates is an attractive technique for fabrication of multi-threshold SSOI-CMOS circuits with high current drive.

Modulation of NiGe∕Ge Schottky barrier height by sulfur segregation during Ni germanidation

We have demonstrated wide-range modulation of Schottky barrier height (SBH) of NiGe∕Ge(100) interfaces by using a valence mending adsorbate, sulfur, segregation during Ni germanidation. Implanted sulfur atoms, segregated during Ni germanidation, are expected to act as dangling bond terminator at the NiGe∕Ge interface. The experimental results show that the strong Fermi level pinning feature of NiGe∕Ge interfaces was alleviated, and SBH of NiGe∕n-Ge(100) gradually decreased from 0.61to0.15eV with an increase in the implanted sulfur dose. This method opens a way to realize Ge channel complementary metal-oxide-semiconductor field-effect transistors with metal source/drain.

High-mobility strained SiGe-on-insulator pMOSFETs with Ge-rich surface channels fabricated by local condensation technique

A new approach to form strained SiGe-on-insulator (SGOI) channel transistors, allowing fabrication of MOSFETs with very high Ge fraction in selected areas on a silicon-on-insulator substrate, is demonstrated. This method consists of epitaxial growth of an SiGe layer with a low Ge fraction and local oxidation processes. An obtained SGOI pMOSFET with a Ge fraction of 0.93 exhibits up to a tenfold enhancement in mobility. It is also found that MOSFETs having strained SGOI channels with thicknesses of less than 5 nm exhibit hole-mobility enhancement factors of over two. These results indicate that the local SGOI channels fabricated by the proposed technique are promising for implementation of high-mobility SiGe or Ge-channel MOSFETs in system-on-chip (SoC) devices.