Shuji Hamada

Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects

In this paper, a new ATPG methodology is proposed to improve the quality of test sets generated for detecting delay defects. This is achieved by integrating timing information, e.g. from standard delay format (SDF) files, into the ATPG tool. The timing information is used to guide the test generator to detect faults through the longest paths in order to improve the ability to detect small delay detects. To avoid propagating faults through similar paths repeatedly, a weighted random method is proposed to improve the path coverage during test generation. During fault simulation, a new fault-dropping criterion, named dropping based on slack margin (DSM), is proposed to facilitate the trade-off between the test set quality and the test pattern count. The quality of the generated test set is measured by two metrics: delay test coverage and SDQL. The experimental results show that significant test quality improvement is achieved when applying timing-aware ATPG with DSM to industrial designs

Invisible delay quality - SDQM model lights up what could not be seen

The quality of delay testing focused on small delay defects is not clear when traditional fault models are used. We therefore evaluated the feasibility of using the statistical delay quality model (SDQM) - which reflects fabrication process quality, design delay quality, test timing accuracy, and test pattern quality - by using a commercial automatic test program generation (ATPG) tool to apply it to a large data set. The SDQM can also provide a measure predicting the defect level of a chip, and by simulating test patterns we show experimentally here that this measure can be calculated within a reasonable CPU time when using a reasonable amount of memory. Because we found when using SDF information to calculate path lengths accurately that the transition test patterns are not good at detecting small delay defects in long paths, a new test algorithm that detects small delay defects should be developed

Evaluation of the statistical delay quality model

In this paper we introduce a quality model that reflects fabrication process quality, design delay margin, and test timing accuracy. The model provides a measure that can predict the level of chip defects that cause delay failure, including marginal delay. We can therefore use the model to make test vectors that are effective in terms of both testing cost and chip quality. The results of experiments using ISCAS89 benchmark data and some large industrial design data reflect various characteristics of our statistical delay quality model.

A Framework of High-quality Transition Fault ATPG for Scan Circuits

This paper presents a framework of high-quality test generation for transition faults in full scan circuits. This work assumes a restricted broad-side testing as a test application method for two-pattern tests where control of primary inputs and observation of primary outputs are restricted. Because we use a modified time expansion model of a circuit-under-test during ATPG and fault simulation, conventional ATPG and fault simulation programs can work with minor change. The proposed ATPG method consists of two algorithms, which are activation-first and propagation-first, and for each fault it is decided which algorithm should be applied. Test patterns are generated such that transition faults with small delay can be detected, i.e. a path for fault excitation and propagation becomes as long as possible. In experimental results we evaluate test patterns generated by the proposed method using SDQM that calculates delay test quality, and show the effectiveness of the proposed method

Not all Delay Tests Are the Same - SDQL Model Shows True-Time

Assessing the effectiveness of transition fault testing by the test coverage is misleading and can result on lower product quality. In reality, the actual timing of the test for each fault determines if a delay defect of a given size is detected or not. Transition tests that use actual circuit timings to create tests with the tightest possible timing detect more defects and have higher test effectiveness for a given test coverage. This paper validates this assertion using a statistical delay quality model (SDQM) model to estimate the statistical delay quality level (SDQL) of several chips. The comparison includes transition tests generated with and without actual circuit timing as a function of the actual timing of the tests for each fault

Recognition of Sensitized Longest Paths in Transition Delay Test

The progress of design and fabrication technologies has led to an increase in small delay failures in systems-on-a-chip. To evaluate the delay testing quality accurately, the authors have already proposed a statistical approach that calculates actual sensitized path lengths that detect small delay defects in the transition delay test. However, the calculation requires a huge amount of CPU time. This paper presents a much more efficient method to calculate the sensitized longest path lengths and experimental results regarding CPU time and accuracy. The experiments show that this calculation method has high speed and high accuracy

Path delay test compaction with process variation tolerance

In this paper we propose a test compaction method for path delay faults in a logic circuit. The method generates a compact set of two-pattern tests for faults on long paths selected with a criterion. While the proposed method generates each two-pattern test for more than one fault in the target fault list as well as ordinary test compaction methods, secondary target faults are selected from the fault list such that many other faults, which may not be included in the fault list, are detected by the test pattern. Even if faults on long paths in a manufactured circuit are not included in the fault list due to a process variation or noise, the compact test set would detect the longer untargeted faults, i.e., the test set has a noise or variation tolerant nature. Experimental results show that the proposed method can generate a compact test set and it detects longer untargeted path delay faults efficiently.

A dynamic test compaction procedure for high-quality path delay testing

We propose a dynamic test compaction procedure to generate high-quality test patterns for path delay faults. While the proposed procedure generates a compact two-pattern test set for paths selected by a path selection criterion, the generated test set would detect not only faults on the selected paths but also faults on many unselected paths. Hence both high test quality by detecting untargeted faults and test cost reduction by reducing test patterns can be achieved. Experimental results show that the proposed procedure could generate a compact test set that detect many untargeted path delay faults certainly, compared with the static test compaction method previously proposed (Kajihara et al., 2005)

A Statistical Quality Model for Delay Testing

SUMMARY In this paper we introduce a statistical quality model fordelay testing that reflects fabrication process quality, design delay margin,and test timing accuracy. The model provides a measure that predicts thechip defect level that cause delay failure, including marginal small delay.We can therefore use the model to make test vectors that are effective interms of both testing cost and chip quality. The results of experiments us-ing ISCAS89 benchmark data and some large industrial design data reflectvarious characteristics of our statistical delay quality model. key words: delay testing, quality model, defect distribution 1. Introduction The progress of fabrication process and design technologyleads to marginal or parametric failures that are caused byresistive shorts or resistive vias [1]. They will occur moreoften and it will be more difficult to screen them effectivelyby the conventional testing methods.Delay testing is regarded as one of the key technologiesfor those problems and has been widely studied to improvetesting effectiveness. Many delay fault models were pro-posed. The transition delay fault model [2] considers thepropagation of lumped delay defects by logical transition tothe observation pins or flip-flops. It is widely used becauseof its high fault coverage, but it cannot detect defects caus-ing delays that are smaller than the test timing. The path de-lay fault model [2] considers the propagation of distributeddelay along a path. It can detect small delay defects, but itis hard to achieve high fault coverage because there is ex-ponential number of paths in a chip. Some longest pathsare selected and tested; however, their coverage is so smallthat the effectiveness is not quantified [2]. A statistical pathselection technique that considers process variation was pro-posed [3]. It is a reasonable approach for practical testing,but its effectiveness is still unknown.There are some papers that address small delay defects.Park et at.[4],[5] give the basic idea that evaluates small de-lay defects. They introduced the delay defect density func-