Seiki Ogura

Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistor

The LDD structure, where narrow, self-aligned n-regions are introduced between the channel and the n+source-drain diffusions of an IGFET to spread the high field at the drain pinchoff region and thus reduce the maximum field intensity, is analyzed. The design is shown, including optimization of the n-dimensions and concentrations and the boron channel doping profile and an evaluation of the effect of the series resistance of the n-regions on device transconductance. Characteristics of experimental devices are presented and compared to those of conventional IGFETs. It is shown that significant improvements in breakdown voltages, hot-electron effects, and short-channel threshold effects can be achieved allowing operation at higher voltage, e.g., 8.5 versus 5 V, with shorter source-drain spacings, e.g., 1.2 versus 1.5 µm. Alternatively, a shorter channel length could be used for a given supply voltage. Performance projections are shown which predict 1.7 × basic device/circuit speed enhancement over conventional structures. Due to the higher voltages and higher frequency operation, the higher performance results in an increase in power which must be considered in a practical design.

Fabrication of high-performance LDDFET's with Oxide sidewall-spacer technology

A fabrication process for the Lightly Doped Drain/Source Field-Effect Transistor, LDDFET, that utilizes RIE produced SiO 2 sidewall spacers is described. The process is compatible with most conventional polysilicon-gated FET processes and needs no additional photomasking steps. Excellent control and reproducibility of the n-region of the LDD device are obtained. Measurements from dynamic clock generators have shown that LDDFETs have as much as 1.9X performance advantage over conventional devices.

A new asymmetrical halo source GOLD drain (HS-GOLD) deep sub-half-micrometer n-MOSFET design for reliability and performance

A novel asymmetrical n-MOSFET device structure has been developed which is suitable, in terms of reliability and performance, for scaling down to the sub-quarter-micron level, without reduction of the supply voltage below 3.5 V. In this structure (HS-GOLD), large-tilt implantation is used to form the gate-overlapped lightly doped drain (GOLD) region at the drain electrode only. A halo (punch-through stopper) is used at the source, but not at the drain. Superior hot-carrier reliability and high punch-through resistance are obtained using this device structure. A reliability-limited supply voltage at 4.2 V is obtained for HS-GOLD n-MOSFETs with effective channel lengths as short as 0.25 mu m. High punch-through resistance is achieved without extreme scaling of S-D (source-drain) junctions and gate oxide (120 AA). The threshold roll-off characteristics suggest that this n-MOSFET structure can be designed with about 0.3 mu m shorter channel length (L/sub eff/=0.15 mu m) while maintaining the 3.5-V supply voltage. Reliable operation of 0.15- mu m n-MOSFETs at 3.5-V supply voltage using the proposed device structure is demonstrated by 2D simulation. >

A half micron MOSFET using double implanted LDD

Double-implanted LDD, which consists of self-aligned p pockets below the n regions in LDD, is introduced to improve both breakdown and short channel effects. Its fabrication and experimental results are presented. The device optimized for a 0.5µm channel and 3.5V supply is discussed.

Elimination of hot electron gate current by the lightly doped drain-source structure

In the LDD structure, narrow self-aligned n-regions are added between the channel and the source/drain of a conventional FET. The resulting device suffers less from high electric field effects than a conventional FET. In particular, it is shown through computer simulations and experimental data that the degradation of device characteristics, due to hot electron injection into the gate insulator, is rendered insignificant by the LDD structure. Consequently a higher operating voltage and/or shorter channel length may be utilized to improve the performance of circuits design with LDD FETs.

Process design for merged complementary BiCMOS

A process sequence was designed to fabricate a fully complementary BiCMOS technology. In this technology, a merged bipolar-FET device structure and common subcollector p-n-p are used to implement a complementary emitter follower circuit, yielding a strong density advantage over conventional BiCMOS logic. The problems associated with the p-n-p subcollector formation, gate oxide protection, base formation, emitter protection and source/drain formation have been addressed. The result is a technology with a process complexity that is well-managed and has high performance.<<ETX>>

Submicron MOSFET performance at liquid nitrogen temperatures

Conclusions of a study on submicron silicon gate MOSFET performance, indicating that 0.5μm devices operating at liquid nitrogen temperatures afford twice the speed and reduced sensitivity to power supply voltage than sub-0.25μm devices at room temperatures, will be discussed. Test devices using double-implanted lightly-doped drains were used in the anaylsis.

Fabrication of extremely thin silicon on insulator for fully-depleted CMOS applications

A technique to produce extremely thin (<1000 A) silicon on insulator (SOI) films for fully-depleted CMOS fabrication is described. The worst-case film thickness uniformity is ±200 A across a 125 mm wafer for a given area factor. This technique utilizes a low temperature plasma enhanced chemical vapor deposition of Si3N4 acting as a chemical-mechanical polish-stop layer. The nitride film thickness is translated into the SOI by chemical-mechanical polishing.