Seng-Pan U

A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS

A 1.2 V 10-bit 100 MS/s Successive Approximation (SA) ADC is presented. The scheme achieves high-speed and low-power operation thanks to the reference-free technique that avoids the static power dissipation of an on-chip reference generator. Moreover, the use of a common-mode based charge recovery switching method reduces the switching energy and improves the conversion linearity. A variable self-timed loop optimizes the reset time of the preamplifier to improve the conversion speed. Measurement results on a 90 nm CMOS prototype operated at 1.2 V supply show 3 mW total power consumption with a peak SNDR of 56.6 dB and a FOM of 77 fJ/conv-step.

Transceiver architecture selection: Review, state-of-the-art survey and case study

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An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC

An 8-b 400-MS/s 2-b-per-cycle (2 b/C) successive approximation register (SAR) analog-to-digital converter (ADC) is fabricated in 65-nm CMOS. With the implementation of a low-power and small-area resistive DAC and associated highly integrated circuit implementation, the proposed SAR ADC achieves rapid conversion rate, low power, and compact area, leading to SNDR of 44.5 dB and SFDR of 54.0 dB, at 400 MS/s with 1.9-MHz input. The measured FOM is 73 fJ/conversion-step at 400 MS/s from 1.2-V supply and 42 fJ/conversion-step at 250 MS/s from a 1-V supply. The active area with the digital calibration is 0.028 mm2.

On the Design of a Programmable-Gain Amplifier With Built-In Compact DC-Offset Cancellers for Very Low-Voltage WLAN Systems

Two circuit techniques adopted in the design of an embedded programmable-gain amplifier (PGA) for very low-voltage (LV) wireless local-area network systems are presented. A switched-current-resistor (SCR) technique minimizes the bandwidth variation and the transient in gain tuning by stabilizing, concurrently, the PGAs feedback factor and quiescent-operating point. Another technique, inside-opamp dc-offset canceller (DOC), embeds inside the PGAs opamp a subthreshold-biased - integrator for extracting its output dc-offset, while negatively feeding the correction (current) signal back to the opamp at an inherent low-impedance node. The resultant main benefits are: 1) the chip area, for realizing the large time constant in dc-offset extraction, is very small and 2) the lower cutoff of the PGA and the DOC-induced nonlinearity and noise are all suppressed by an amount of the loop gain in closed-loop formation. A 1-V three-stage 52-dB gain range PGA reinforcing such two techniques was designed and fabricated in a 3.3-V 0.35- CMOS process. It consumes 7.4 mW of power while measuring gain-switching transient and IIP3. The means of the lower and upper cutoffs (averaged over 52-dB gain steps) are 2.25 kHz and 17.1 MHz, respectively.

Split-SAR ADCs: Improved Linearity With Power and Speed Optimization

This paper presents the linearity analysis of a successive approximation registers (SAR) analog-to-digital converters (ADC) with split DAC structure based on two switching methods: conventional charge-redistribution and Vcm-based switching. The static linearity performance, namely the integral nonlinearity and differential nonlinearity, as well as the parasitic effects of the split DAC, are analyzed hereunder. In addition, a code-randomized calibration technique is proposed to correct the conversion nonlinearity in the conventional SAR ADC, which is verified by behavioral simulations, as well as measured results. Performances of both switching methods are demonstrated in 90 nm CMOS. Measurement results of power, speed, and linearity clearly show the benefits of using Vcm-based switching.

A 0.024mm 2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS

The successive-approximation (SA) algorithm is traditionally used for low-bandwidth applications because it requires n clock cycles or more to obtain n-bit resolution. However, the use of modern nanometer CMOS technologies and special design solutions overcome the speed limit, enabling conversion rates in the hundreds of MHz with very low power consumptions [1]. This design uses the successive-approximation method to obtain 8b up to 400MS/s with very low power using a 1.2V supply. Key features of the architecture are a resistive DAC and a 2b-per-cycle conversion with interpolated sampling front-ends and shift registers. A cross-coupled bootstrapping network is also implemented to alleviate the signal-dependent clock feed-through. The very compact layout leads to a silicon area of 0.024 mm2.

A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC

A 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC architecture is proposed, where the ADCs front-end is built with a 5b binary-search ADC, shared by two time-interleaved 6b SAR ADCs in the 2nd-stage. The design prevents the use of opamp that causes large power dissipation. Besides, a process insensitive asynchronous logic is proposed to further reduce the delay of SA loop. The ADC was fabricated in 65nm CMOS and achieves 54.6dB SNDR at 170MS/s with only 2.3mW of power consumption, leading to a FoM of 30.8fJ/conversion-step.

Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC

This brief presents the architectural concept of an optimal subranging ADC, obtained with the cascade of a Flash and a SAR, which is also explored through its practical design and experimental confirmation. The solution doubles the optimal speed of operation of the SAR ADCs at the relative low power cost of a low-resolution Flash. The digital correction method and a capacitor-based DAC ensure nondemanding requirements for the Flash. The effectiveness of the architecture is verified in a 90-nm CMOS chip whose active core area is 0.64 mm2. The ADC obtains a peak SNDR of 51.8 dB and SFDR of 63.4 dB at 90 MS/s consuming 13.5 mW from a 0.9-V supply. Measured DNL and INL are 0.87 LSB and 1.55 LSB, respectively.

A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation

This paper presents a time-interleaved pipelined-SAR ADC with on-chip offset cancellation technique. The design reuses the SAR ADC to perform offset cancellation, thus saving calibration costs. The inter-stage gain of 8 is implemented in a 6-bit capacitive DAC with a flip-around operation. A capacitive attenuation used in both the first and second DACs significantly reduces the power dissipation and optimizes conversion speed. The detailed circuit implementation of the subthreshold op-amp is discussed, and the possible limits caused by nonidealities are analyzed for a proper correction in the design. These include the inter-stage-gain error and various channel mismatches of offset, gain, and timing. Measurements of a 65-nm CMOS prototype operating at 160 MS/s and 1.1-V supply show an SNDR of 55.4 dB and 2.72 mW total power consumption.

20.4 A 123-phase DC-DC converter-ring with fast-DVS for microprocessors

Inspired by The Square of Vatican City, a fully integrated step-down switched-capacitor DC-DC converter ring with 100+ phases is designed with a fast dynamic voltage scaling (DVS) feature for the microprocessor in portable or wearable devices. As shown in Fig. 20.4.1, this symmetrical ring-shaped converter surrounds its load in the square and supplies the on-chip power grid, such that a good quality power supply can be easily accessed at any point of the chip edges. There are 30 phases on the top edge and 31 phases on each of the other 3 edges, making 123 phases in total. The phase number and unit cell dimensions of this architecture can easily be adjusted to fit the floor plan of the load. The pads of the converter-ring are placed at the corners, and will not affect the pads of the load. Moreover, by using the proposed VDD-controlled oscillator (VDDCO), the frequency of which is controlled by varying its supply voltage, a hitherto unexplored feature of the multiphase DC-DC architecture is exposed: the control-loop unity gain frequency (UGF) could be designed to be higher than the switching frequency.