Kun-tack Lee

Effect of pad surface roughness on material removal rate in chemical mechanical polishing using ultrafine colloidal ceria slurry

In this paper, effect of ultrafine ceria (UFC) particle of which size is as small as 20 nm on CMP performance was investigated. Compared to conventionally used 100 nm abrasive particle which is made by calcination process, almost 80% scratch reduction was obtained by using UFC. However, a UFC slurry showed unstable material removal rate behavior from less than 200 Å/min to over 2000 Å/min, depending on polishing pad surface characteristics. As pad surface roughness increases, oxide removal rate using UFC drops abruptly to less than 200 Å/min. In order to use UFC for scratch reduction, the pad surface roughness optimization is necessary to avoid a sudden drop in the removal rate. This study gives a possible boundary for pad surface roughness for UFC application for CMP.

A study of swing-curve physics in diffraction-based overlay

With the increase of process complexity in advanced nodes, the requirements of process robustness in overlay metrology continues to tighten. Especially with the introduction of newer materials in the film-stack along with typical stack variations (thickness, optical properties, profile asymmetry etc.), the signal formation physics in diffraction-based overlay (DBO) becomes an important aspect to apply in overlay metrology target and recipe selection. In order to address the signal formation physics, an effort is made towards studying the swing-curve phenomena through wavelength and polarizations on production stacks using simulations as well as experimental technique using DBO. The results provide a wealth of information on target and recipe selection for robustness. Details from simulation and measurements will be reported in this technical publication.

Effect of Ashing, Strip and Annealing Process on the Dopant Concentration of Silicon

Introduction Silicon has been used successfully for semiconductor material because it can have a high degree of purity at a low cost, and shows the good mechanical, chemical and electrical properties. In the respect of electrical properties, the pure silicon is an insulator, thus the ion implantation process is necessary to make insulating silicon into semiconductor. Generally, the electrical properties of silicon based semiconductors are determined by the characteristics of dopant. Hence the study for the change of dopants concentration in following process such as ashing, strip, and annealing, is very important. (Shown in Figure 1.) In this study, we will discuss about the loss of dopant by strip process using fluorine-based stripper and annealing.

Metrology target design simulations for accurate and robust scatterometry overlay measurements

Overlay metrology target design is an essential step prior to performing overlay measurements. This step is done through the optimization of target parameters for a given process stack. A simulation tool is therefore used to improve measurement performances. This work shows how our Metrology Target Design (MTD) simulator helps significantly in the target design process. We show the role of film and Optical CD measurements in improving significantly the fidelity of the simulations. We demonstrate that for various target design parameters we are capable of predicting measured performance metrics by simulations and correctly rank various designs performances.