Bon-young Koo

Characterization of threshold voltage instability after program in charge trap flash memory

We investigated threshold voltage shifts after program pulse in charge trap flash memory by measuring drain current changes. We have found threshold voltage shifts can be characterized as a function of not only the materials of tunnel oxide, trap layer, blocking layer, but also physical parameters like device size and electrical measurement environment such as program voltage target and gate bias voltage. This approach can identify the root cause of initial threshold voltage shifts in charge trap flash memory devices.

Effects of plasma nitridation on the electrical properties of nitrided oxide gate dielectric for DRAM application

We reduced the gate tunneling current by seven times and suppressed NBTI using plasma nitridation-induced re-oxidation (PIROX). In plasma nitrided gate oxynitride, the nitrogen concentration at the MOS interface is determined after plasma nitridation process, which affects the electrical and physical properties of gate oxynitride. To facilitate the control of nitrogen concentration at the MOS interface, an additional re-oxidation process is needed, but decreasing the nitrogen concentration. In this paper, the plasma nitridation process is proposed that realizes simultaneously the nitridation and re-oxidation without an additional process and the decrease of nitrogen concentration. The control of nitrogen concentration and the amount of re-oxidation under high pressure process improves the gate tunneling current, mobility, and NBTI.

Characterization of novel SiO 2 /a-Si/a-SiOx tunnel barrier engineered oxide

We suggested the heterogeneously stacked oxide (HSO) for the future tunnel oxide of high density NAND flash memory. HSO has a structure of SiO2/a-Si/a-SiOx using the concept of tunnel barrier engineering. By employing HSO tunnel barrier, it was possible to fabricate the tunnel oxide, which is thicker physically and thinner electrically than the single layer tunnel oxide. The bandgap of a-SiOx can be modified, which made it possible to achieve tunnel barrier engineering without employing high-k material. By reducing the erase voltage, the reliabilities of NAND flash memory was improved.

Highly-reliable NAND flash memory using Al 2 O 3 -inserted inter-poly dielectric

The improvement of device performances has been achieved successfully through OAO IPD EOT scaling, which shows that OAO IPD is applicable to sub-40nm devices which require aggressive scaling of IPD EOT. Charge loss of OAO IPD at high temperature is explained by thermionic emission of alumina traps. Trap profiles of alumina were obtained by monitoring Vth shift above 100°C. OAO IPD shows good data retention at room temperature, which is consistent with trap profiles.

Front-end-of-line (FEOL) optimization for high-performance, high-reliable strained-Si MOSFETs; from virtual substrate to gate oxidation

Front-end-of-line (FEOL) process parameters including virtual substrate (Si/Si/sub 1-x/Ge/sub x/), shallow-trench-isolation (STI) process, and gate oxidation have strong effects on performance and reliability of strained-Si MOSFETs such as gate oxide integrity (GOI), threshold voltage (V/sub TH/ roll-off, reliability behavior including junction breakdown and device isolation characteristics. It is found that gate oxide integrity can be improved by 1 order of magnitude by applying low-temperature, plasma oxidation process as compared with thermal oxidation, junction leakage and device isolation characteristics can be improved by 1 order of magnitude and by two times, respectively, by using low-defect virtual substrate and further defect-curing process, and parameters related with STI process such as thin SiN layer and oxide densification temperature must be optimized both to reduce junction leakage current and to improve device performance such as Ion-Ioff characteristics.