Seong-Do Kim

A 4-GHz All Digital PLL With Low-Power TDC and Phase-Error Compensation

This paper presents a 4-GHz all-digital fractional-N PLL with a low-power TDC operating at low-rate retimed reference clocks, a compensator preventing big phase-error downfalls, and a loop settling monitor. Two retimed reference clocks, nCKR and pCKR, are employed in the TDC to estimate the fractional phase error between the low-rate reference and high-rate oscillator clocks. Applying the retimed reference clocks does not only reduce a dynamic power in its delay chain, but simplify a fractional phase-error correction. The phase-error compensator is introduced to avoid big phase-error downfalls caused by large output glitches originating from a high-speed accumulator. In addition, a loop-settling monitor is invented to allow the DCO operation mode to be shifted seamlessly and fast. By consuming 9.6 mW, the ADPLL achieves -97 dBc in-band phase noise, - 38 dBc/Hz integrated noise, and 740 ns settling time.

A 4-GHz all digital fractional-N PLL with low-power TDC and big phase-error compensation

This paper presents an all-digital fractional-N PLL with a low-power TDC operating at the retimed reference clock. Two retimed reference clocks are employed to implement the proposed TDC estimating the fractional phase error between the reference clock and CKV clock. The application of the retimed reference clocks to TDC does not only reduce dynamic power in TDC delay inverter chain, but also simplify εr estimation including a new Tv calculation algorithm. Also, phase-error compensation block is presented to compensate for the big phase-error change due to timing skew in the output bits produced from variable-phase counter. And loop settling scanning block is invented to shift DCO operation mode and additionally decrease PLL channel switching time for frequency hopping applications. The proposed all-digital PLL represents − 36dBc integrated phase noise (1kHz – 20MHz), 778fs rms jitter, 9.6mW power consumption. The channel switching time of the ADPLL is measured as 630nsec.

A 77GHz CMOS array receiver, transmitter and antenna for low cost small size automotive radar

A 77GHz CMOS 4-channels receiver, transmitter with 3-outputs and array antenna architecture is proposed for low cost/small size automotive radar system, and implemented by using 65nm CMOS technology and LTCC substrate. Measured performance of CMOS transceiver, which included useful functions such as dual operation of long/short range detection, I/Q signal process and gain attenuation when near target detection, shows comparable performances to that of commercial SiGe radar chips. Especially, the transmitter consumes one third lower power compared to SiGe chips. These results confirm that it may be a promising candidate for low cost and small size car radar system.

Human detection based on the condition number in the non-stationary clutter environment using UWB impulse radar

In this paper, we propose a human detection method in non-stationary clutter environment using ultrawideband (UWB) impulse radar. We treat the foliage swaying in the wind as the non-stationary clutter. It is observed that the signal from the human body is more correlated than the signal from the non-stationary clutter. The method based on the condition number of correlation matrix is used to distinguish the human from the non-stationary clutter. The experimental results show that the proposed method shows better detection probability than the conventional method.

A 4-GHz low-power TDC-based all digital PLL having 9.6mW and 1.2ps rms jitter

This paper presents a 4-GHz ADPLL with low-power TDC using two low-rate retimed reference clocks (pCKR, nCKR) to measure the fractional phase error between the reference clock edge and DCO clock edge. The application of the retimed reference clocks enables TDC to avoid metastability of its sampling register as well as alleviate large dynamic power of its delay inverter chain. A mode-decision block is also proposed to generate suitable control signals for accomplishing seamless movement of DCO operation mode. The proposed ADPLL achieves − 95 dBc/Hz in-band phase noise and 1.2ps rms jitter, consuming 9.6mW.

Design of a Fully Integrated Low Power CMOS RF Tuner Chip for Band-III T-DMB/DAB Mobile TV Applications

This paper describes a fully integrated CMOS low-IF mobile-TV RF tuner for Band-III T-DMB/DAB applications. All functional blocks such as low noise amplifier, mixers, variable gain amplifiers, channel filter, phase locked loop, voltage controlled oscillator and PLL loop filter are integrated. The gain of LNA can be controlled from -10 dB to +15 dB with 4-step resolutions. This provides a high signal-to-noise ratio and high linearity performance at a certain power level of RF input because LNA has a small gain variance. For further improving the linearity and noise performance we have proposed the RF VGA exploiting Schmoock`s technique and the mixer with current bleeding, which injects directly the charges to the transconductance stage. The chip is fabricated in a 0.18 um mixed signal CMOS process. The measured gain range of the receiver is -25~+88 dB, the overall noise figure(NF) is 4.02~5.13 dB over the whole T-DMB band of 174~240 MHz, and the measured IIP3 is +2.3 dBm at low gain mode. The tuner rejects the image signal over maximum 63.4 dB. The power consumption is 54 mW at 1.8 V supply voltage. The chip area is .