Seon-Ho Han

An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/a converter

An 800-MHz low-power direct digital frequency synthesizer (DDFS) with an on-chip digital-to-analog (D/A) converter is presented. The DDFS consists of a phase accumulator, two phase-to-sine converters, and a D/A converter. The high-speed operation of the DDFS is enabled by applying parallelism to the phase-to-sine converter and by including a D/A converter in a single chip. The on-chip D/A converter saves delay and power consumption due to interchip interconnections. The DDFS considerably reduces power consumption by using several low-power techniques. The pipelined parallel accumulator consumes only 22% power of a conventional pipelined accumulator with the same throughput. The quad line approximation (QLA) and the quantization and error ROM (QE-ROM) minimize the ROM to generate a sine wave. The QLA saves 4 bits of the sine amplitude by approximating the sine function with four lines. The QE-ROM quantizes the ROM data by magnitude and address and then it stores the quantized values and the quantization errors separately. The ROM size for a 9-bit sine output is only 368 bits. A DDFS chip is fabricated in a 0.35-/spl mu/m CMOS process. It consumes only 174 mW at 800 MHz with 3.3 V. The chip core area is 1.47 mm/sup 2/. The spurious-free dynamic range (SFDR) is 55 dBc.

A CMOS IF transceiver with 90 dB linear control VGA for IMT-2000 application

A prototype IF transceiver has been integrated in 0.35 /spl mu/m CMOS technology. The chip includes VGAs and mixers for IMT-2000. The VGAs are controlled continuously in linear dB by using a proposed quasi-exponential gain control method. Measurements show that both VGAs have over 90 dB dynamic range and 9.5 dB NF in receiver. The -3 dB frequencies of the receiver and transmitter are 250 MHz and 430 MHz, respectively. Thus, the transceiver can adapt to PCS as well as IMT-2000 for potential dual-band application. With a single 3.0 V power supply, the VGAs and mixers consume 16 mA and 6 mA, respectively.

A low power and low noise frequency synthesizer with a integrated quadrature VCO

A frequency synthesizer including a integrated quadrature VCO and a few novel circuits is presented in a 0.18 um CMOS technology. A 16/17 dual modulus prescaler operates up to 5.1 GHz due to the fast (about 10 GHz) operation of the proposed complementary clocking (CC) dynamic flip-flop. Also, a phase frequency detector (PFD) utilizing the charge pump current feedback, generates low spurious tones irrespective of the temperature or supply variations. The measured reference spur is less than -120 dBc with a second order loop-filter of which bandwidth equals f/sub REF//50. The measured out- and in-band phase noise of the quadrature VCO is -140 dBc@8 MHz and -82dBc@10 kHz, respectively. With a 1.8 V power supply, the current consumption of the overall frequency synthesizer is only 7.5 mA except 50 /spl Omega/ driving buffers.

A Low-Power Interference-Tolerance Wideband Receiver for 802.11af/ah Long-Range Wi-Fi With Post-LNA Active

A low-power interference-tolerance wideband receiver with post-LNA active N-path filter for RF channel selection is proposed for 802.1af/ah long-range Wi-Fi standards. By leveraging gain, noise, and filtering characteristics among the wideband LNA, high-Q active N-path filter, and reconfigurable analog baseband circuits, the proposed receiver achieves high gain, low noise, and high linearity with low power dissipation. The receiver provides narrow-bandwidth RF filtering with a small chip area. Implemented in a 40-nm CMOS process with the chip size of 1.1 mm <inline-formula> <tex-math notation=LaTeX>

N

times2.25

-Path Filter

</tex-math></inline-formula> mm, the full receiver shows a conversion gain of 84 ± 1 dB and achieves noise figure from 3.4 to 3.9 dB in subgigahertz frequency bands. The measured in-band IIP3, out-of-band IIP3, and out-of-band IIP2 are −5.9, −0.5, and +62.5 dBm, respectively. The proposed receiver dissipates an average power of 41 mW.

A 41dB Gain Control Range 6 th -Order Band-Pass Receiver Front-End Using CMOS Switched FTI

A 41dB gain control range 6 th -order band-pass receiver front-end (RFE) using CMOS switched frequency translated impedance (FTI) is presented in a 40 nm CMOS technology. The RFE consists of a frequency tunable RF band-pass filter (BPF), IQ gm cells, and IQ TIAs. The RF BPF has wide gain control range preserving constant filter Q and pass band flatness due to proposed pre-distortion scheme. Also, the RF filter using CMOS switches in FTI blocks shows low clock leakage to signal nodes, and results in low common mode noise and stable operation. The baseband IQ signals are generated by combining baseband Gm cells which receives 8-phase signal outputs down-converted at last stage of FTIs in the RF BPF. The measured results of the RFE show 36.4 dB gain and 6.3 dB NF at maximum gain mode. The pass-band IIP3 and out-band IIP3@20 MHz offset are -10 dBm and +12.6 dBm at maximum gain mode, and +14 dBm and +20.5 dBm at minimum gain mode, respectively. With a 1.2 V power supply, the current consumption of the overall RFE is 40 mA at 500 MHz carrier frequency.

A fully integrated receiver front-end reconfigured by PLL

A fully integrated receiver front-end, reconfigured by a frequency locking scheme using a PLL, is implemented in a 0.18 /spl mu/m triple-well CMOS technology. The receiver front-end is composed of a discretely tunable low noise amplifier (DT-LNA), a quadrature down mixer, and a discretely and continuously tunable frequency synthesizer (DCT-FS) with an integrated DCT-VCO. The front-end measured performances are 2-2.75 GHz tuning range by about 50 MHz steps, 40 dB voltage gain, -25 dBm IIP3, 2.1-2.7 dB DSB NF. The synthesizer features a phase noise of -80 dBc/Hz at in-band and -120 dBc/Hz at 1 MHz offset. The receiver front-end consumes 30 mA from a 1.8 V supply.