Seong-Je Kim

Impact of the top silicon thickness on phonon-limited electron mobility in (110)-oriented ultrathin-body silicon-on-insulator n-metal-oxide-semiconductor field-effect transistors

We investigated through a theoretical simulation how the phonon-limited electron mobility in both (110)- and (100)-oriented ultrathin-body (UTB) silicon-on-insulator (SOI) n-metal-oxide-semiconductor field-effect transistors (MOSFETs) depends on the top silicon thickness within a range from 20to2nm. No electron mobility enhancement was observed in (110) UTB SOI n-MOSFETs when the top silicon thickness was around 5nm, unlike in (100) UTB n-MOSFETs. Thus, electron mobility in (110) UTB SOI n-MOSFETs decreased with top silicon thickness, particularly in the range below 10nm. We attributed the electron mobility degradation in (110) UTB SOI n-MOSFETs within the top silicon thickness range below 10nm to a decrease in the effective width of the inversion layer and an increase in intravalley acoustic phonon scattering, rather than to less carrier repopulation due to less band splitting between two- and fourfold valleys.

Comparative study of self-heating effect on electron mobility in nano-scale strained silicon-on-insulator and strained silicon grown on relaxed SiGe-on-insulator n-metal–oxide–semiconductor field-effect transistors

From the viewpoint of the silicon thickness limit for mobility enhancement in a strained Si channel, we investigated the difference in the self-heating effect on electron mobility between strained silicon-on-insulator (sSOI) and strained Si grown on relaxed SiGe-on-insulator (e-Si SGOI) n-metal–oxide–semiconductor field-effect transistors (MOSFETs) as a function of silicon thickness. We found, for the first time, by numerical simulation that when considered with the presence of self-heating in the silicon thickness range from 5 to 10 nm, the reduction in the mobility enhancement ratio of sSOI n-MOSFETs is less than that of e-Si SGOI n-MOSFETs by numerical simulation. In addition, we confirmed that the quantum size effect, occurring at the peak mobility value of a 3 nm silicon thickness, disappeared in sSOI n-MOSFETs but was suppressed in e-Si SGOI n-MOSFETs. Therefore, we propose that an sSOI n-MOSFET is a more promising device than a e-Si SGOI n-MOSFET for high-performance devices with a design rule of less than 45 nm.

Dependence of memory margin of Cap-less memory cells on top Si thickness

We investigated the dependence of Cap-less memory on top of silicon with a thickness between 15.5 and 72.3 nm. It was confirmed that the memory margin depends on the impact ionization rate associated with the increased conduction current density and the decreased lateral electric field as the top silicon thickness increases. In particular, we observed that the maximum memory margin is 61 μA at a 45 nm top silicon thickness, where the impact ionization rate is maximized. Consequently, we obtained the optimal top silicon thickness of 45 nm for Cap-less memory cells operating in fully depleted silicon-on-insulator n-metal-oxide-semiconductor field-effect transistors.

Dependence of temperature and self-heating on electron mobility in ultrathin body silicon-on-insulator n-metal-oxide-semiconductor field-effect transistors

We investigated the dependence of temperature and self-heating on electron mobility in ultrathin body fully depleted silicon-on-insulator n-metal-oxide-semiconductor field-effect transistors as a function of silicon thickness by analyzing their electron states and electrical characteristics. We found that as the temperature increases, electron mobility decreases regardless of the silicon thickness. We also found that there is a less decrease when the silicon thickness is less than 3 nm than when it is greater than 3 nm. This is because there is a greater electron occupancy in a twofold valley. We demonstrated that the quantum size-effect, i.e., the higher electron mobility in silicon with a thickness less than 3 nm caused by the size-effect, can be eliminated by self-heating.

A multi-level capacitor-less memory cell fabricated on a nano-scale strained silicon-on-insulator

A multi-level capacitor-less memory cell was fabricated with a fully depleted n-metal-oxide-semiconductor field-effect transistor on a nano-scale strained silicon channel on insulator (FD sSOI n-MOSFET). The 0.73% biaxial tensile strain in the silicon channel of the FD sSOI n-MOSFET enhanced the effective electron mobility to ∼ 1.7 times that with an unstrained silicon channel. This thereby enables both front- and back-gate cell operations, demonstrating eight-level volatile memory-cell operation with a 1 ms retention time and 12 µA memory margin. This is a step toward achieving a terabit volatile memory cell.

Capacitor-less memory-cell fabricated on nanoscale unstrained Si layer on strained SiGe layer-on-insulator

We investigated the effect of the presence of strained SiGe layer inserted between unstrained Si and buried oxide layer and the Ge concentration in strained SiGe layer on the memory margin of capacitor-less memory-cell. We observed that memory margin of unstrained Si on strained SiGe-on-insulator capacitor-less memory-cells increases with the Ge concentration of the strained SiGe layer and obtained memory margin at the Ge concentration of 19 at% that was 3.2 times larger than that at the silicon-on-insulator capacitor-less memory-cell. This enhancement was due to the potential-barrier lowering increasing exponentially with the Ge concentration resulting from higher hole confinement in spite of the reduction in the saturated drain current.

Dependence of Electrical Characteristics on Si Thickness and Ge Concentration for Unstrained Si Grown on Strained SiGe-on-Insulator n-Metal–Oxide–Semiconductor Field-Effect Transistor

The dependencies of the electrical characteristics of n-metal–oxide–semiconductor field-effect transistors (n-MOSFETs) on the nano-scale Si thickness (<20 nm) and Ge concentration for unstrained Si grown on strained SiGe-on-insulator were investigated. As the Si thickness decreased, the electron mobility decreased more significantly than the strained Si n-MOSFET grown on relaxed SiGe-on-insulator (SGOI). In addition, the electron mobility decreased with increasing the Ge concentration, contrary to strained Si SGOI n-MOSFET.

The impact of wafer nanotopography on threshold voltage variation in NAND flash memory cells fabricated with poly-silicon chemical mechanical polishing

Based on simulation, the threshold voltage (VT) variation for NAND flash memory cells fabricated with the self-alignment of the poly-silicon floating gate is expected to be related to the peak-to-valley value (PV) of wafer nanotopography. After chemical and mechanical polishing (CMP) of the poly-silicon floating gate, the PV of the remaining height of the poly-silicon floating gate linearly increased with the PV of wafer nanotopography. As a result, the VT variation linearly increased with the PV of the remaining height of the poly-silicon floating gate after CMP. These simulation results show, in particular, that the VT variation of NAND flash memory cells induced by wafer nanotopography becomes larger and larger as the device size becomes smaller and smaller.

Optimal Channel Ion Implantation for High Memory Margin of Capacitor-Less Memory Cell Fabricated on Fully Depleted Silicon-on-Insulator

The effect of channel doping concentration on the memory margin of capacitor-less (Cap-less) memory cells fabricated on fully depleted silicon-on-insulator (SOI) n-metal–oxide–semiconductor field-effect transistors (MOSFETs) was investigated. It was observed that the memory margin of Cap-less memory cells is significantly varied by the channel doping concentration, i.e., it increases with doping concentrations up to 1.4 ×1017 cm-3 and then decreases with higher doping concentrations. In particular, at a concentration of 1.4 ×1017 cm-3 it increased 1.8 times compared with that at 1.5 ×1015 cm-3. This gives rise to speculation that the memory margin of Cap-less memory cells fabricated on fully depleted SOI n-MOSFETs can be increased by enlarging the lateral electric field and can be decreased by reducing the current density. These results suggest that a higher memory margin in Cap-less memory cells can be obtained by optimizing channel doping concentration in fully depleted SOI n-MOSFETs.