Gon-Sub Lee

Multilevel nonvolatile small-molecule memory cell embedded with Ni nanocrystals surrounded by a NiO tunneling barrier.

Four-level nonvolatile small-molecule 4F(2) memory cells were developed with a sandwiched device structure consisting of an upper Al electrode, upper small-molecule layer (Alq(3), aluminum tris(8-hydroxyquinoline)), Ni nanocrystals surrounded by NiO tunneling barrier, lower small-molecule layer, and bottom Al electrode. In particular, an in situ O(2)-plasma oxidation process following Ni evaporation was developed to produce uniformly stable 10 nm Ni nanocrystals surrounded by a NiO tunneling barrier embedded in the small-molecule layer. They presented a memory margin (I(on)/I(off) ratio) of approximately 1 x 10(3), a retention time of more than 10(5) s, an endurance of more than 5 x 10(2) erase-and-program cycles, and multilevel cell (MLC) operation, being a terabit nonvolatile memory-cell. A vertically double-stacked 4F(2) multilevel nonvolatile memory cell was also developed, showing a memory margin of approximately 1 x 10(3) in both the top and bottom memory cells and eight-level cell operation.

Crystal Originated Particle Induced Isolation Failure in Czochralski Silicon Wafers

The presence of crystal originated particle (COP) on the 64 Mbyte dynamic random access memory (DRAM) device isolation region causes the current path between neighboring transistors, resulting in COP induced isolation failure. The probability of the COP induced isolation failure occurrence depends on the COP size; i.e., larger COP size leads to higher probability of failure. In addition, failure strongly depends on the process condition applied to the isolation structure, for example, the nitride film thickness; i.e., thicker nitride film results in a less probability of failure. Furthermore, failure also depends on the isolation structure itself; i.e., higher probability of the COP induced isolation failure follows local oxidation of silicon (LOCOS) > polysilicon space LOCOS (PSL) > selective polysilicon oxidation (SEPOX).

Low-cost and flexible ultra-thin silicon solar cell implemented with energy-down-shift via Cd0.5Zn0.5S/ZnS core/shell quantum dots

Flexible ultra-thin silicon (∼30 μm thickness) solar cells implemented with an energy-down-shift layer showed stable flexible and twistable characteristics. In particular, spin-coating Cd0.5Zn0.5S/ZnS core/shell quantum dots (QDs) on the cells enhanced the PCE by ∼0.7% through an energy-down-shift effect that enhanced the external quantum efficiency in the UV light region. In addition, the cells demonstrated an excellent bending fatigue performance because their PCE levels were sustained at ∼12.4% after 5000 bending cycles under a strain of ∼5.72%.

Flexible conductive-bridging random-access-memory cell vertically stacked with top Ag electrode, PEO, PVK, and bottom Pt electrode

Flexible conductive-bridging random-access-memory (RAM) cells were fabricated with a cross-bar memory cell stacked with a top Ag electrode, conductive polymer (poly(n-vinylcarbazole): PVK), electrolyte (polyethylene oxide: PEO), bottom Pt electrode, and flexible substrate (polyethersulfone: PES), exhibiting the bipolar switching behavior of resistive random access memory (ReRAM). The cell also exhibited bending-fatigue-free nonvolatile memory characteristics: i.e., a set voltage of 1.0 V, a reset voltage of -1.6 V, retention time of >1 × 10(5) s with a memory margin of 9.2 × 10(5), program/erase endurance cycles of >10(2) with a memory margin of 8.4 × 10(5), and bending-fatigue-free cycles of ∼1 × 10(3) with a memory margin (I(on)/I(off)) of 3.3 × 10(5).

Dependence of crystal nature on the gettering efficiency of iron and nickel in a Czochralski silicon wafer

The gettering efficiency of both iron and nickel in a Czochralski silicon wafer strongly depends on the crystal nature, i.e. an interstitial silicon dominant crystal or a vacancy dominant crystal. After heat treatment of dynamic random access memory, iron is mainly precipitated in the vacancy dominant crystal region rather than the interstitial silicon dominant crystal region, since the density of silicon oxide precipitate in the vacancy dominant crystal region is approximately two orders higher than that in the interstitial silicon dominant crystal region. This indicates that the mechanism of iron gettering is associated with relaxation gettering by silicon oxide precipitates. Otherwise, nickel silicides at the wafer surface are dominantly produced in the interstitial silicon crystal region, while nickel is chiefly precipitated at silicon oxide precipitates in the vacancy dominant crystal region. Also, this result demonstrates that the mechanism of nickel gettering is associated with relaxation gettering by silicon oxide precipitates, since silicon oxide precipitates are virtually not produced in the interstitial silicon dominant crystal region. A super silicon wafer designed for proximity gettering by silicon oxide precipitates shows a superior gettering efficiency for iron and nickel via the elimination of the memorized crystal nature.

Dependence of temperature and self-heating on electron mobility in ultrathin body silicon-on-insulator n-metal-oxide-semiconductor field-effect transistors

We investigated the dependence of temperature and self-heating on electron mobility in ultrathin body fully depleted silicon-on-insulator n-metal-oxide-semiconductor field-effect transistors as a function of silicon thickness by analyzing their electron states and electrical characteristics. We found that as the temperature increases, electron mobility decreases regardless of the silicon thickness. We also found that there is a less decrease when the silicon thickness is less than 3 nm than when it is greater than 3 nm. This is because there is a greater electron occupancy in a twofold valley. We demonstrated that the quantum size-effect, i.e., the higher electron mobility in silicon with a thickness less than 3 nm caused by the size-effect, can be eliminated by self-heating.

Nature of Surface and Bulk Defect Induced by Low Dose Oxygen Implantation in Separation by Implanted Oxygen Wafers

Two new metrologies have been proposed to characterize unknown surface and bulk defects in separation by implanted oxygen (SIMOX) wafers. They included the following: i) laser scattering particle counter plus coordinated atomic force microscope (AFM) and Cu-decoration for defect isolation and ii) cross-sectional transmission electron microscope (TEM) foil preparation using focused ion beam (FIB) and TEM investigation for defect morphology observation. Three types of surface defects were found and described as follows: i) a hole with a locally thinned top silicon layer (Park Defect A), ii) a hole formed locally without either a silicon or a buried oxide layer (Park Defect B), and iii) a hole formed with both a locally thinned top silicon and a buried oxide layer (Park Defect C). In addition, a bulk defect was found to occur as locally distributed square-shaped pits accompanied by the disappearance of the buried oxide layer (isolation defect). All surface and bulk defects in SIMOX wafers originate from oxide particle generation by electrostatic discharge and mechanical abrasion between the wafer and the pin of the wafer holder during oxygen ion implantation.

Nanoscale CuO solid-electrolyte-based conductive-bridging-random-access-memory cell operating multi-level-cell and 1selector1resistor

Nanoscale (∼28 nm) non-volatile multi-level conductive-bridging-random-access-memory (CBRAM) cells are developed by using a CuO solid-electrolyte, providing a Vset of ∼0.96 V, a Vreset of ∼−1.5 V, a ∼1 × 102 memory margin, ∼3 × 106 write/erase endurance cycles with 100 μs AC pulse, ∼6.63 years retention time at 85 °C, ∼100 ns writing speed, and multi-level (four-level) cell operation. Their non-volatile memory cell performance characteristics are intensively determined by studying material properties such as crystallinity and poly grain size of the CuO solid-electrolyte and are found to be independent of nanoscale memory cell size. In particular, the CuO solid-electrolyte-based CBRAM cell vertically connecting with p/n/p-type oxide (CuO/IGZO/CuO) selector shows the operation of 1S(selector)1R(resistor), demonstrating a possibility of cross-bar memory-cell array for realizing terabit-integration non-volatile memory cells.

Impact of tungsten contamination on the sensing margin of a CMOS image sensor cell

We investigated the impact of tungsten contamination on minority-carrier recombination lifetime, the photodiode dark/photo current and sensitivity of a pinned photodiode, and the sensing margin of a CMOS image sensor (CIS) cell. After an intentional tungsten contamination and followed by driving at 800 °C for 30 min, tungsten contaminant were located from the surface to p- and n-type regions of a photodiode. The tungsten contamination degraded minority-carrier recombination life-time and the dark current and sensitivity of a pinned photodiode; i.e., there was a good correlation between the minority recombination lifetime and the sensitivity of a photodiode. As a result, tungsten contamination directly degraded the sensing margin of a CIS cell photodiode; i.e., it decreased with increasing tungsten contaminant concentration.

Effect of nanohole structure on pyramid textured surface on photo-voltaic performance of silicon solar cell

We investigated how the nanohole structure on a {111} pyramid textured surface affected the photovoltaic performance of silicon solar cells by varying nanohole depth. During the effective minority carrier recombination lifetime, the surface reflectance decreased with increasing nanohole depth, showing a trade-off relationship. The power conversion efficiency (PCE) of silicon solar cells with the {111} pyramid textured surface peaked at a specific nanohole depth, i.e., 0.43% PCE enhancement (3.32% enhancement relative to a reference cell) was obtained at the nanohole depth of 94.8 nm.