Kyung-Chang Ryoo

Three-Dimensional nand Flash Architecture Design Based on Single-Crystalline STacked ARray

Various critical issues related with 3-D stacked nand Flash memory are examined in this paper. Our single-crystalline STacked ARray (STAR) has many advantages such as better scalability, possibility of single-crystal channel, less sensitivity to 3-D interference, stable virtual source/drain characteristic, and more extendability over other stacked structures. With STAR, we proposed a unit 3-D structure, i.e., “building.” Then, using this new component, 3-D block and full chip architecture are successfully designed. For the first time, the structure and operation methods of the “full” array are considered. The fully designed 3-D nand Flash architecture will be the novel solution of reliable 3-D stacked nand Flash memory for terabit density.

Highly Reliable 256Mb PRAM with Advanced Ring Contact Technology and Novel Encapsulating Technology

Advanced ring type technology and encapsulating scheme were developed to fabricate highly manufacturable and reliable 256Mb PRAM. Very uniform BEC area was prepared by the advanced ring type technology in which core dielectrics were optimized for cell contact CMP process. In addition, relatively high set resistance was stabilized from encapsulating Ge2Sb2Te5 (GST) stack with blocking layers, thus giving rise to a wide sensing window. These advanced ring type and encapsulating technologies can provide great potentials of developing high density 512Mb PRAM and beyond

Ge2Sb2Te5 Confined Structures and Integration of 64 Mb Phase-Change Random Access Memory

Phase-change random access memory is considered a potential challenger for conventional memories, such as dynamic random access memory and flash memory due to its numerous advantages. Nevertheless, high reset current is the ultimate problem in developing high-density phase-change random access memory (PRAM). We focus on the adoption of Ge2Sb2Te5 confined structures to achieve lower reset currents. By changing from a normal to a GST confined structure, the reset current drops to as low as 0.8 mA. Eventually, our integrated 64 Mb PRAM based on 0.18 µm CMOS technology offers a large sensing margin: Rreset ~200 kΩ and Rset ~2 kΩ, as well as reasonable reliability: an endurance of 1.0×109 cycles and a retention time of 2 years at 85°C.

Highly Reliable Ring-Type Contact for High-Density Phase Change Memory

An advanced bottom electrode contact (BEC) was successfully developed for reliable high-density 256 Mb phase-change random access memory (PRAM) using a ring-type contact scheme. This advanced ring-type BEC was prepared by depositing very thin TiN films inside a contact hole, after which core dielectrics were uniformly filled into the TiN-deposited contact hole. Using this novel contact scheme, it was possible to reduce reset current while maintaining a low set resistance and a uniform cell distribution. Thus, it has been clearly demonstrated that the use of the ring-type contact technology is very feasible for high-density PRAM beyond 256 Mb.

Effects of conducting defects on resistive switching characteristics of SiNx-based resistive random-access memory with MIS structure

In this work, the effects of conducting defects on resistive switching characteristics of SiNx-based resistive random-access memory (RRAM) have been investigated. Two types of RRAM devices having metal–insulator–silicon layer configuration were fabricated. One is the device with SiNx as the resistive switching layer deposited by plasma-enhanced chemical vapor deposition (PECVD), and the other has the SiNx layer prepared by low-pressure chemical vapor deposition (LPCVD). The device cell deposited by LPCVD (LP-SiNx cell afterward) demonstrated superior uniformity of switching parameters and better endurance cycles compared with the device cell deposited by PECVD (PE-SiNx cell afterward).

Novel U-Shape Resistive Random Access Memory Structure for Improving Resistive Switching Characteristics

We firstly propose a novel U-shape resistive cell structure which is the best fit for generating low power resistive random access memory (RRAM) with forming-less process. We find that irregular resistive switching behavior in the initial transition and the characteristics associated with it. Controlling the conducting filament (CF) dimension and deposition orientation of resistive material are expected to reduce the distribution and forming voltage, which enables low power RRAM to be feasible without forming state. Simple fabrication flow and device performances are also evaluated in the aspect of forming-less process. Numerical simulation is performed using random circuit breaker model (RCB) to confirm the proposed structure.

Ring Contact Electrode Process for High Density Phase Change Random Access Memory

It is very important to maintain stable cell uniformity for reliable operation and wide sensing margin since the writing current is mainly governed by the bottom electrode contact (BEC) size which is especially sensitive to small process variation. In order to accomplish low writing current with uniform cell distribution, advanced storage module technology using ring type BEC was proposed. Using this, it was possible to achieve flat and uniform BEC, which results in a wide sensing margin and high manufacturability. Finally, we firstly fabricated advanced ring type contact structure and firstly evaluated based on high density 256 Mbytes phase change random access memory (PRAM) with small cell size technologies.

Areal and Structural Effects on Oxide-Based Resistive Random Access Memory Cell for Improving Resistive Switching Characteristics

A new technical improvement in understanding the resistive switching characteristics of unipolar resistive random access memory (RRAM) is investigated. It is possible to minimize reset current (IRESET), set voltage variation, and forming voltage (VFORMING), which results in a wide sensing margin and high density applications by using a conducting filament (CF) minimized structure up to a 10 nm technology node. Its structural advantages enable IRESET to be tuned with excellent manufacturability. Numerical simulation is also performed using a random circuit breaker (RCB) model, showing that the proposed structure elucidates the resistive switching improvement.

Performance Impact of a Slower Main Memory: A case study of STT-MRAM in HPC

In high-performance computing (HPC), significant effort is invested in research and development of novel memory technologies. One of them is Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) --- byte-addressable, high-endurance non-volatile memory with slightly higher access time than DRAM. In this study, we conduct a preliminary assessment of HPC system performance impact with STT-MRAM main memory with recent industry estimations. Reliable timing parameters of STT-MRAM devices are unavailable, so we also perform a sensitivity analysis that correlates overall system slowdown trend with respect to average device latency. Our results demonstrate that the overall system performance of large HPC clusters is not particularly sensitive to main-memory latency. Therefore, STT-MRAM, as well as any other emerging non-volatile memories with comparable density and access time, can be a viable option for future HPC memory system design.

Uniformity improvement by optimization of switching interface in bi-layer unipolar RRAM structure for low power new memory application

RRAM is very promising due to many fascinating advantages as follows; fast writing/reading time, low programming power and multi bit storage for high density up to tera bit memory are possible [1]. But it is very difficult to satisfy all best resistive switching characteristics. There is a trade-off between reset current (IRESET) and forming voltage (VFORMING) in single layered cell structure as shown in fig. 1 (a). Fig. 1 (b) shows the initial resistance (RINITIAL) as a function of reset resistance (RRESET) and set resistance (RSET) by using our fabricated NiO based unipolar RRAM cell. We have reported that VFORMING increases if RINITIAL is high enough, therefore it proves that RINITIAL needs to be lowered in order to lower operating condition [2]. However there is also a trade off. If RINITIAL is sufficiently low, sensing margin which means reset/set resistance ratio is also reduced. So, new ideas for satisfying both resistive switching conditions are needed. Figure 2 shows the typical I-V curves of forming (a) and reset/set switching (b) based on single layered unipolar RRAM structure by using RCB model [3] and figure 3 shows the illustration of bi layered RRAM cell structure. Lower layer (2ND resistive layer) is acting as forming assistance layer for low power consumption. Upper layer (1ST resistive layer) is used for controlling reset/set switching. Because resistive switching occurs at cell interface, interface engineering is very critical for improving resistive switching uniformity. Figure 4 illustrates the detailed tested metal — insulator-metal (MIM) cell structure. Charged particle which is source of CF path such as oxygen vacancy and metallic ion in resistive cell can be defined as conductive defect. Conductive defect fraction is varied from 0.05 (lower layer) to 0.025 (upper layer), respectively. Conductive defect fraction of reference cell is 0.05. The each layer rules and their actions for bi-layered RRAM cell structure are summarized in table 2. Figure 5 shows the statistical analysis of VFORMING (a) and VSET (b) characteristics with various cell conditions. Lower VFORMING is addressed in single layered cell due to its larger amount of conductive defects, but in case of 5nm thickness of upper layer (split 1) cell, mean value of forming voltage (VFORMING_μ) difference is only 0.26V.