Moongyu Jang

High speed Flash Memory and 1T-DRAM on dopant segregated Schottky barrier (DSSB) FinFET SONOS device for multi-functional SoC applications

A novel dopant segregated Schottky barrier (DSSB) FinFET SONOS device is demonstrated in terms of multi functioning in a high speed NAND-type flash memory and capacitorless 1T-DRAM. In addition, a novel program mechanism that uses energy band engineered hot electrons (EBEHE) energized by sharp energy band bending at the edge of source/drain (S/D) is proposed for a high speed flash memory programming operation. A short program time of 100 ns and a low program voltage of 12 V yield a Vth shift of 3.5 V and a retention time exceeding 10 years. For multi functioning, the operation of a capacitorless 1T-DRAM is also demonstrated with a partially silicided DSSB in the same device.

A 50-nm-gate-length erbium-silicided n-type Schottky barrier metal-oxide-semiconductor field-effect transistor

The theoretical and experimental current–voltage characteristics of 50-nm-gate-length erbium-silicided n-type Schottky barrier metal-oxide-semiconductor field-effect transistors (SB-MOSFETs) are discussed. The manufactured 50-nm-gate-length n-type SB-MOSFET shows large on/off current ratio with low leakage current less than 10−4 μA/μm. The saturation current is 120 μA/μm when drain and gate voltage is 1 and 3 V, respectively. The experimental current–voltage characteristics of 50-nm-gate-length n-type SB-MOSFET are fitted using newly developed theoretical model. From the theoretical analysis, the off- and on-current is mainly attributed to the thermionic and tunneling current, respectively. The decrease of tunneling distance at silicon/silicide Schottky junction with the increase of drain voltage gives the increase of tunneling current. This phenomenon is explained by using drain-induced Schottky barrier thickness thinning effect.

A novel TFT with a laterally engineered bandgap for of 3D logic and flash memory

A d̲opant s̲egregated S̲chottky b̲arrier (DSSB) TFT SONOS device is demonstrated for the application of 3D TFT logic devices and flash memory. To apply the DSSB to 3D TFT flash memory, a novel spacer-free structure is successfully implemented. The DSSB TFT SONOS shows a good distribution of programmed VT by one-time programming with high-speed (a VT shift of 2.9 V @ 32 ns) due to the use of a unique local injection of carriers from the DSSB S/D junctions and it is not affected by grain boundaries. Moreover, the program speed is accelerated by reduction of the fin width owing to the enhanced field.

Characterization of erbium-silicided Schottky diode junction

Trap density, lifetime, and the Schottky barrier height of erbium-silicided Schottky diode are evaluated using equivalent circuit method. The extracted trap density, lifetime, and Schottky barrier height for hole are determined as 1.5/spl times/10/sup 13/ traps/cm/sup 2/, 3.75 ms and 0.76 eV, respectively. By using the developed method, the interface of the Schottky diode can be evaluated quantitatively.

Characteristics of erbium-silicided n-type Schottky barrier tunnel transistors

The current–voltage characteristics of erbium-silicided n-type Schottky barrier tunnel transistors (SBTTs) are discussed. The n-type SBTTs with 60 nm gate lengths shows typical transistor behaviors in drain current to drain voltage characteristics. The drain current on/off ratio is about 105 at low drain voltage regime in drain current to gate voltage characteristics. However, the on/off ratio tends to decrease as the drain voltage increases. From the numerical simulation results, the increase of off-current is mainly attributed to the thermionic current and the increase of drain current is mainly attributed to the tunneling current, respectively. This phenomenon is explained by using drain induced Schottky barrier thickness thinning effect.

SOI single-electron transistor with low RC delay for logic cells and SET/FET hybrid ICs

We report on a successful fabrication of silicon-based single-electron transistors (SETs) with low RC time constant and their applications to complementary logic cells and SET/field-effect transistor (FET) hybrid integrated circuit. The SETs were fabricated on a silicon-on-insulator (SOI) structure by a pattern-dependent oxidation (PADOX) technique, combined with e-beam lithography. Drain conductances measured at 4.2 K approach large values of the order of microsiemens, exhibiting Coulomb oscillations with peak-to-valley current ratios /spl Gt/1000. Data analysis with a probable mechanism of PADOX yields their intrinsic speeds of /spl sim/ 2 THz, which is within an order of magnitude of the theoretical quantum limit. Incorporating these SETs as basic elements, in-plane side gate-controlled complementary logic cells and SET/FET hybrid integrated circuits were fabricated on an SOI chip. Such an in-plane structure is very efficient in the Si fabrication process, and the side gates adjacent to the electron island could easily control the phase of Coulomb oscillations. The input-output voltage transfer, characteristic of the logic cell, shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2 K. The SET/FET hybrid integrated circuit consisting of one SET and three FETs yields a high-voltage gain and power amplification with a wide-range output window for driving the next circuit. The small SET input gate voltage of 30 mV is finally converted to 400 mV, corresponding to an amplification ratio of 13.

Analysis of Schottky Barrier Height in Small Contacts Using a Thermionic-Field Emission Model

Young Ha Hwang et al. 381 We analyze the performance of a telecommunications management network (TMN) system using models of networks of queues, Jackson’s theorem, and simulation. TMN systems for managing public asynchronous transfer mode (ATM) networks generally have a four-level hierarchical structure consisting of a network management system, a few element management systems (EMSs), and several pairs of agents and ATM switches. We construct a Jackson’s queuing network and present formulae to calculate its performance measures: distributions of queue lengths and waiting times, mean message response time, and maximum throughput. We perform a numerical analysis and a simulation analysis and compare the results.

Simulation of Schottky barrier tunnel transistor using simple boundary condition

The current–voltage characteristics of a Schottky barrier tunnel transistor (SBTT) are simulated by considering the internal voltage drop at the Schottky barrier and using the current continuity condition between the tunneling and channel current. The numerical results show typical behaviors as can be found in many experimental results. From these results, a significantly higher threshold voltage is expected for the SBTT compared to the conventional metal–oxide–semiconductor field-effect transistors, because of the suppression of the tunneling current at low gate voltage. For the nanometer-size device application, a metal gate should be used to decrease the threshold voltage.

Analysis of Transconductance

This paper experimentally investigates the unique behavior of transconductance (gm) in the Schottky-barrier metal-oxide-semiconductor field-effect transistors (SB-MOSFETs) with various silicide materials. When the Schottky-barrier height (SBH) or a scaling parameter is not properly optimized, a peculiar shape of gm is observed. Thus, gm can be used as a novel metric that exhibits the transition of the carrier injection mechanisms from a thermionic emission (TE) to thermally assisted tunneling (TU) in the SB-MOSFETs. When the local maximum point of gm is observed, it can be expected that an incomplete transition occurs between TE and TU in SB-MOSFETs. When a dopant-segregation (DS) technique is implemented in the SB-MOSFETs, however, the carrier injection efficiency from the source to the channel is significantly improved, although the SBH is not minimized. As a consequence, the peculiar shape of the gm disappears, i.e., a complete transition from TE to TU can be enabled by the DS technique.

(g_{m})

Using a Green’s function method based on an elastic wave equation, the effects of surface roughness and the nanowire-contact interface scattering on phonon thermal conductivity are studied at low temperatures. It is found that the interface geometry between a nanowire and its contacts affects the transmission function at small energies related to the gapless modes and it gives rise to deviated results from the universal conductance. It is also shown that the surface roughness is crucial in the suppression of phonon thermal conductivity with reducing the nanowire size by averaging the transmission function over the rough-surface configurations. Furthermore, the phonon mean free path is proportional to the ratio of the correlation length and roughness heights quadratically as well as the cross-section area of the nanowire.