Serdar Manakli

Complementary dose and geometrical solutions for electron beam direct write lithography proximity effects correction: application for sub-45-nm node product manufacturing

After the successful results obtained in the last few years, electron beam direct write (EBDW) lithography for use in integrated circuit manufacturing has now been demonstrated. However, throughput and resolution capabilities need to be improved to push its interest for fast cycle production and advanced research and development applications. In this way, the process development needs good patterns dimensional accuracy, i.e., a better control of the proximity effects caused by backscattering electrons and others phenomenon. In this work, the limitations of the dose modulation method are investigated through the change of dose number steps and the use of a more accurate point spread function. To continue reducing feature sizes, a method to provide a complementary correction to the dose modulation solution is proposed. This rule-based electron beam proximity correction, or REBPC, provides good results down to 40 nm.

MAGIC: a European program to push the insertion of maskless lithography

With the willingness of the semiconductor industry to push manufacturing costs down, the mask less lithography solution represents a promising option to deal with the cost and complexity concerns about the optical lithography solution. Though a real interest, the development of multi beam tools still remains in laboratory environment. In the frame of the seventh European Framework Program (FP7), a new project, MAGIC, started January 1st 2008 with the objective to strengthen the development of the mask less technology. The aim of the program is to develop multi beam systems from MAPPER and IMS nanofabrication technologies and the associated infrastructure for the future tool usage. This paper draws the present status of multi beam lithography and details the content and the objectives of the MAGIC project.

Combination multiple focal planes and PSM for sub 120 nm node with KrF lithography: study of the proximity effects

In optical lithography, the use of multiple focal planes with different energy and focus improves the photolithography performances like the Depth of Focus (DOF) and the Energy Latitude (EL). We have chosen to use a symmetrical double exposure (symmetrical in focus) with equal energy, an attenuated (6%) phase shift mask and the standard KrF photolithography process in the study of 180 nm holes. The ASM 5500 / 700 and / 900 steppers make this double exposure possible. The study of the process window versus the distance between the two focal planes (DF ) shows that the multiple focal planes technique generates proximity effects namely increases the difference between dense holes Critical Dimension (CD) and isolated one for the same parameters (energy, focus and DF ). We study the evolution of these proximity effects for KrF lithography and propose solutions to minimise them.

ArF imaging with off-axis illumination and subresolution assist bars: a compromise between mask constraints and lithographic process constraints

The insertion point for the first scattering bar is a key point in the development of a process using assist features, because this semi dense feature will determine the overall depth of focus of the process. A study of the parameters, which influence the choice of this insertion point, has been performed using a 0.63 NA 193 nm scanner for a 100 nm CD target after litho. The impact of the scattering bar on: Depth of Focus, Energy Latitude, Mask Error Enhancement Factor, printability, and the effect of scattering bar line width variation on main feature described by a parameter called AFMEEF will be discussed in this paper. The optimal insertion point for the first scattering bar will strongly depend on the litho-graphic process and the mask parameters. A model is proposed to determine the optimal insertion point, as function of the dose, focus budget, minimal allowed scatterbar width, and mask CD dispersion for both scattering bars and main features.

Cell projection use in maskless lithography for 45nm and 32nm logic nodes

Due to the ever-increasing cost of equipment and mask complexity, the use of optical lithography for integrated circuit manufacturing is increasingly more complex and expensive. Recent workshops and conferences in semiconductor lithography underlined that one alternative to support sub-32nm technologies is mask-less lithography option using electron beam technology. However, this direct write approach based on variable shaped beam principle (VSB) is not sufficient in terms of throughput, i.e. of productivity. New direct write techniques like multibeam systems are under development, but these solutions will not be mature before 2012. The use of character/cell projection (CP) on industrial VSB tools is the first step to deal with the throughput concerns. This paper presents the status of the CP technology and evaluates its possible use for the 45nm and 32nm logic nodes. It will present standard cell and SRAM structures that are printed as single characters using the CP technique. All experiments are done using the Advantest tool (F3000) which can project up to 100 different cells per layer. Cell extractions and design have been performed with the design and software solution developed by D2S. In this paper, we first evaluate the performance gain that can be obtained with the CP approach compared to the standard VSB approach. This paper also details the patterning capability obtained by using the CP concept. An evaluation of the CD uniformity and process stability is also presented. Finally this paper discusses about the improvements of this technique to address high resolution and to improve the throughput concerns.

High throughput maskless lithography: low voltage versus high voltage

The beam energy is a driving design parameter for electron beam lithography systems. To be able to compare the differences of low kV (5 kV) and high kV (100 kV) for a high-throughput system the limitations of both types of systems are evaluated. First the effect on the CD uniformity and throughput is analyzed. For any shot noise limited system the dose that is needed to obtain a required CD uniformity can be calculated. This dose depends on the total spot size and the efficiency of the electrons in the resist. For a smaller spot less dose is required than for a large spot. The current in a single beam is also determined by the spot size. A larger spot has more current. With these parameters an optimization of the required dose, spot size and single beam current can be made. It is found that although for high kV it is easier to create a small spot with a high current the low resist-exposure efficiency of the high-energy electrons limits the throughput, because the required dose is large. It is also found that for 10 wafers per hour multiple lenses or columns are required. For practical reasons (a high kV lens cannot be made as small as a low kV lens) there is a clear preference for the use of low energy in high-throughput systems. Another aspect that is crucial in the lithography process is the overlay. One of the main differences between high and low energy systems is the power that is dissipated in the wafer and the resulting error due to expansion. It is found that for both energies wafer heating is an issue, but for low kV there seem to be solutions, while for high kV the problem is 30 times bigger.

Electron beam direct write process development for sub 45nm CMOS manufacturing

Electron Beam Direct Write (EBDW) lithography represents a low cost and a rapid way to start basic studies for advance devices and process developments. Patterning for sub-45nm node technology requires the development of high performance processes. Different alternatives for the improvement of EBDW lithography are investigated in this paper for the ASIC manufacturing on 300mm wafer size. Among them, process development has been tuned for clear field equivalent level to improve both line width roughness by monitoring post applied bake conditions, and both process window by specific design correction. Concerning dark field level, process resolution has been improved by a shrinkage technique.

Gate imaging for 0.09-μm logic technology: comparison of single exposure with assist bars and the CODE approach x

xIn order to address some specific issues related to gate level printing of the 0.09μm logic process, the following mask and illumination solutions have been evaluated. Annular and Quasar illumination using binary mask with assist feature and the CODE (Complementary Double Exposure) technique. Two different linewidths have been targeted after lithography: 100nm and 80nm respectively for lowpower and high-speed applications. The different solutions have been compared for their printing performance through pitch for Energy Latitude, Depth of Focus and Mask Error Enhancement Factor. The assist bar printability and line-end control was also determined. For printing the 100nm target, all tested options can be used, with a preference for Quasar illumination for the gain in Depth of Focus and MEEF. For the 80nm target however, only the CODE technique with Quasar give sufficient good results for the critical litho parameters.

Optimization of the depth of focus based on the analysis of the diffraction orders in the pupil plane

The evolution of the depth of focus has been studied using a simple geometrical analysis of the diffraction orders in the pupil plane. This analysis is based on the observation that the diffraction orders participating to the interactions must be symmetrical with respect to the optical axis. The center of the gravity of the areas of the different diffraction orders captured by the pupil is evaluated as a function of pitch, numerical aperture and wavelength. Analytical expressions have been derived. They give which illumination settings (partial coherence) optimise the DOF for conventional, annular and quadrupole illuminations. The impact of the diffraction orders on the evolution of the DOF through pitch curve was also studied. The appearance of a peak in the DOF versus pitch curve, for annular and quadrupole cases is caused by the perfect symmetry between the diffracted waves interacting together.

Complementary double-exposure technique (CODE): a way to print 80-nm gate level using a double-exposure binary mask approach

To follow the accelerating ITRS roadmap, microprocessor and DRAM manufacturers have introduced the Alternating Phase shift mask (Alt.PSM) resolution enhancement technique (RET) in order to be able to print the gate level on sub 130nm devices. This is done at very high mask costs, a long cycle time and poor guarantee to get defect free masks. S. Nakao has proposed a new RET. He showed that sub 0.1um features could be printed with good process latitudes using a double binary mask printing technique. This solution is very interesting, but is applicable to isolated structures only. To overcome this limitation, we have developed an extension to this technique called CODE. This combines Nakaos technique and the use of assist features removed in a second subsequent exposure. This new solution enables us to print isolated as well as dense features on advanced devices using two binary masks. This paper will describe all the steps required to develop the CODE application. (1) Determination of the optimal optical settings, (2) Determination of optimal assist feature size and placement, (3) Layout rules generation, (4)Application of the layout rules to a complex layout, using the Mentor Graphics Calibre environment, (5) Experimental verification using a 193nm 0.63NA scanner.