Pierre-Jerome Goirand

Combination multiple focal planes and PSM for sub 120 nm node with KrF lithography: study of the proximity effects

In optical lithography, the use of multiple focal planes with different energy and focus improves the photolithography performances like the Depth of Focus (DOF) and the Energy Latitude (EL). We have chosen to use a symmetrical double exposure (symmetrical in focus) with equal energy, an attenuated (6%) phase shift mask and the standard KrF photolithography process in the study of 180 nm holes. The ASM 5500 / 700 and / 900 steppers make this double exposure possible. The study of the process window versus the distance between the two focal planes (DF ) shows that the multiple focal planes technique generates proximity effects namely increases the difference between dense holes Critical Dimension (CD) and isolated one for the same parameters (energy, focus and DF ). We study the evolution of these proximity effects for KrF lithography and propose solutions to minimise them.

ArF imaging with off-axis illumination and subresolution assist bars: a compromise between mask constraints and lithographic process constraints

The insertion point for the first scattering bar is a key point in the development of a process using assist features, because this semi dense feature will determine the overall depth of focus of the process. A study of the parameters, which influence the choice of this insertion point, has been performed using a 0.63 NA 193 nm scanner for a 100 nm CD target after litho. The impact of the scattering bar on: Depth of Focus, Energy Latitude, Mask Error Enhancement Factor, printability, and the effect of scattering bar line width variation on main feature described by a parameter called AFMEEF will be discussed in this paper. The optimal insertion point for the first scattering bar will strongly depend on the litho-graphic process and the mask parameters. A model is proposed to determine the optimal insertion point, as function of the dose, focus budget, minimal allowed scatterbar width, and mask CD dispersion for both scattering bars and main features.

Gate imaging for 0.09-μm logic technology: comparison of single exposure with assist bars and the CODE approach x

xIn order to address some specific issues related to gate level printing of the 0.09μm logic process, the following mask and illumination solutions have been evaluated. Annular and Quasar illumination using binary mask with assist feature and the CODE (Complementary Double Exposure) technique. Two different linewidths have been targeted after lithography: 100nm and 80nm respectively for lowpower and high-speed applications. The different solutions have been compared for their printing performance through pitch for Energy Latitude, Depth of Focus and Mask Error Enhancement Factor. The assist bar printability and line-end control was also determined. For printing the 100nm target, all tested options can be used, with a preference for Quasar illumination for the gain in Depth of Focus and MEEF. For the 80nm target however, only the CODE technique with Quasar give sufficient good results for the critical litho parameters.

Optimization of the depth of focus based on the analysis of the diffraction orders in the pupil plane

The evolution of the depth of focus has been studied using a simple geometrical analysis of the diffraction orders in the pupil plane. This analysis is based on the observation that the diffraction orders participating to the interactions must be symmetrical with respect to the optical axis. The center of the gravity of the areas of the different diffraction orders captured by the pupil is evaluated as a function of pitch, numerical aperture and wavelength. Analytical expressions have been derived. They give which illumination settings (partial coherence) optimise the DOF for conventional, annular and quadrupole illuminations. The impact of the diffraction orders on the evolution of the DOF through pitch curve was also studied. The appearance of a peak in the DOF versus pitch curve, for annular and quadrupole cases is caused by the perfect symmetry between the diffracted waves interacting together.

Complementary double-exposure technique (CODE): a way to print 80-nm gate level using a double-exposure binary mask approach

To follow the accelerating ITRS roadmap, microprocessor and DRAM manufacturers have introduced the Alternating Phase shift mask (Alt.PSM) resolution enhancement technique (RET) in order to be able to print the gate level on sub 130nm devices. This is done at very high mask costs, a long cycle time and poor guarantee to get defect free masks. S. Nakao has proposed a new RET. He showed that sub 0.1um features could be printed with good process latitudes using a double binary mask printing technique. This solution is very interesting, but is applicable to isolated structures only. To overcome this limitation, we have developed an extension to this technique called CODE. This combines Nakaos technique and the use of assist features removed in a second subsequent exposure. This new solution enables us to print isolated as well as dense features on advanced devices using two binary masks. This paper will describe all the steps required to develop the CODE application. (1) Determination of the optimal optical settings, (2) Determination of optimal assist feature size and placement, (3) Layout rules generation, (4)Application of the layout rules to a complex layout, using the Mentor Graphics Calibre environment, (5) Experimental verification using a 193nm 0.63NA scanner.

Device specific characterization of yield limiting pattern geometries by combining layout profiling with high sensitivity wafer inspection

This paper reports on a new approach to capture the impact of marginal pattern geometries on occurrence of systematic yield-limiting defects. Layout profiling and Hot-Spot checking techniques were used to mark new incoming device layout for regions that approached the known marginal pattern geometries at a varying degree of match quality. Further these regions were translated into inputs for advanced high-sensitivity wafer inspection tools of the Broadband Plasma family with Context Based Inspection capability. Finally specially prepared wafers for this device were exercised through high sensitivity targeted inspections to assess the defect occurrence at each of the regions picked based on layout profiling. Finally all the data was assimilated into an easy-to-interpret visual which shows where the printing margins are smallest on this device.

Impact of synchronization errors on overlay and CD control

Quality of exposures on Step&Scan systems highly depends on stages synchronization. While scanning, wafer and reticle stages must have same relative speed (4x ratio) and directions. In this paper, we investigate the tolerance to lateral vibrations of 0.18micrometers and 0.12micrometers gate patterning respectively on an ASML PAS5500/750E scanner (KrF) and a PAS5500/900 scanner (ArF) exposure tools. Results should be given both on the MA impact on overlay and the MSD effect on CD control. But, as no adapted experimental method has been found to correlate overlay degradation to induced MA and then confirm the theory that 1nm of MA induces 1nm of translation, only results on CD control will be discussed, including lateral MSD impact on nominal CD variations, process latitudes degradations and intrafield CD dispersion. In particular, we will show that MSD effect on CD strongly differs from 248nm imaging process to 193nm one.

Improving lithography intra wafer CD for C045 implant layers using STI thickness feed forward

In this paper we performed an analysis of various data collection preformed on C045 production lots in order to assess the influence of STI oxide layers on the CD uniformity of implant photolithography layers. Our final purpose is to show whether the DOSE MAPPERTM software option for interfiled dose correction available on ASML scanners combined with a run-to-run feed-forward regulation loop could improve global CD uniformity on C045 implants layers. After a brief presentation of the C045 implants context the results of the analysis are presented : swing curves, process windows analysis, and intra-die CD measurements are presented. The conclusion of the analysis is that it is not possible, in the current C045 industrial environment, to use a robust and general method of interfield dose correction in order to achieve a better global CD uniformity.

32-nm SOC printing with double patterning, regular design, and 1.2 NA immersion scanner

Resolution Enhancement Techniques (RET) are inherently design dependent technologies. To be successful the RET strategy needs to be adapted to the type of circuit desired. For SOC (system on chip), the three main patterning constraints come from: -Static RAM with very aggressive design rules specially at active, poly and contact -transistor variability control at the chip level -random layouts The development of regular layouts, within the framework of DFM, enables the use of more aggressive RET, pushing the required k1 factor further than allowed with existing RET techniques and the current wavelength and NA limitations. Besides that, it is shown that the primary appeal of regular design usage comes from the significant decrease in transistor variability. In 45nm technology a more than 80% variability reduction for the width and the length of the transistor at best conditions, and more than 50% variability reduction though the process window has been demonstrated. In addition, line-end control in the SRAM bitcell becomes a key challenge for the 32nm node. Taking all these constraints into account, we present the existing best patterning strategy for active and poly level of 32nm : -dipole with polarization and regular layout for active level -dipole with polarization, regular layout and double patterning to cut the line-end for poly level. These choices have been made based on the printing performances of a 0.17&mgr;m2 SRAM bitcell and a 32nm flip-flop with NA 1.2 immersion scanner.

Overlay improvement through lot-based feed-forward: applications to various 28nm node lithography operations

We introduced a very simple overlay feed forward correction based on lot data issued from previous lithography operations. Simple method for correction factor optimization was also proposed. We applied this method in various cases based on 28nm node early production: implants lithography on 248nm tools, contact holes double patterning on 193nm immersion tool, and we also tried to improve contact holes patterning based on 248nm lithography data. All analysis were based on early production 28nm node data mixing 28LP and 28FDSOI technologies. We first optimized the correction based on our simple approach, and then compute the dispersion of all linear overlay parameters. Maximum modeled overlay error was also computed. In most cases we obtained significant improvements. The interest of such a very simple approach that requires reduced software development and allows simple implementation was thus demonstrated.