Sergei Drizlikh

Effects of wafer bow and warpage on performance of electrostatic chucks in high volume manufacturing

This paper presents the learning, the authors gained when dealing with back side pressure faults (BSPF) on 200 mm interconnect deposition tools equipped with minimum contact area (MCA) electrostatic chucks (ESC). It was found that BSPFs occurred more likely on chucks running mostly BiCMOS product. BiCMOS product was four times more susceptible to experience this fault than CMOS due to higher wafer bow and warpage which were traced to recrystallization of backside polysilicon at RTP emitter anneal. Moreover, a cost-effective rework scheme was implemented to prolong the life of ESCs. Long term solution of reducing wafer bow and warpage process is also being pursued

Case of via resistance increase during thermal cycle

We report on a case of via resistance increase after process induced thermal cycles. Evidence of volume expansion at via bottom is shown on cross sections, with complete disconnect between the W plug and ARC TiN in worst case. The problem is traced to interaction between Fluorine implanted into TiN ARC during the oxide overetch step and Ti portion of the via liner. When liner Ti is treated by N/sub 2/ plasma prior to CVD TiN deposition, the problem is reduced.

In Line Wafer Mapping TXRF Analysis Supporting Process Improvements and Process Development

Wafer mapping TXRF is used as a process optimization tool in metal etch, silicon nitride deposition and chemical mechanical polish.