Douglas Brisbin

Hot carrier reliability of N-LDMOS transistor arrays for power BiCMOS applications

This paper evaluates the hot carrier performance of n-channel lateral DMOS (N-LDMOS) transistors. The N-LDMOS has been the common choice for the driver transistor in high voltage (20-30 V) smart power applications. These high drain voltages potentially make N-LDMOS hot carrier degradation an important reliability concern. This paper focuses on the hot carrier test methodology and geometry effects in N-LDMOS transistor arrays. This paper differs from previous work in that it describes for the first time the HC performance of N-LDMOS transistor arrays rather than discrete devices and discusses an N-LDMOS failure mode not yet addressed in the literature.

Substrate Current Independent Hot Carrier Degradation in NLDMOS Devices

Automotive and telecom applications often require voltages in the 20-30V range. These circuits combine high performance CMOS with a high voltage MOS transistor. A possible choice for the high voltage device is an n-channel lateral DMOS transistor (NLDMOS). An advantage of an NLDMOS transistor is that it can be easily integrated within existing technologies without significant process changes. In most cases, though, the drain drift implant must be optimized to meet breakdown voltage and hot carrier reliability requirements. This paper focuses on understanding anomalous hot carrier results obtained from an NLDMOS transistor whose drain drift implant dose was varied

Impact of NBTI and HCI on PMOSFET threshold voltage drift

Abstract Negative bias temperature instability (NBTI) induced PMOSFET parameter degradation is a serious reliability concern in advanced analog and mixed signal technologies. In this paper, Vt-mismatch shift due to NBTI in a cascode current mirror is examined. The impact of NBTI and hot-carrier injection (HCI) on threshold voltage degradation and subsequent damage recovery during annealing is also studied. Finally the influence of channel length, gate voltage, drain voltage and damage recovery on conventional NBTI and HCI DC lifetime extrapolation is characterized with the impact on analog applications highlighted.

Design optimization of N-LDMOS transistor arrays for hot carrier lifetime enhancement

Todays power management devices often require operation in the 20-30 V range. These applications combine a high performance BiCMOS process with a power lateral n-channel DMOS (N-LDMOS) driver. To obtain high drive currents and low on-resistance, LDMOS devices are often implemented in transistor arrays. Because of the high voltages and currents applied to these arrays, hot carrier (HC) degradation is a real reliability concern. This paper differs from previous work in that it discusses for the first time one- and two-dimensional aspects of LDMOS transistor array layout on HC performance and introduces a novel LDMOS transistor layout featuring a drain ring that substantially improves the arrays HC performance.

A New Fast-Switching NBTI Characterization Method That Determines Subthreshold Slope Degradation

For PMOSFET devices, negative bias temperature instability (NBTI) is a serious reliability concern. Because of recovery effects, careful stress and measurement methods must be used to determine threshold voltage degradation. These methods typically assume that mobility and subthreshold slope (SubSlp) degradation are minimal. Recent papers have pointed out that this assumption may not be valid. This paper discusses for the first time a unique fast-switching NBTI measurement technique that alternates between two VGS measurement conditions to determine the SubSlp versus stress time. From these measurements, the effect of SubSlp degradation on VT degradation can be accurately determined, and results are compared to the standard techniques.

Anomalous Safe Operating Area and Hot Carrier Degradation of NLDMOS Devices

Automotive and telecom applications often require voltages in the 20-30 V range. These circuits combine high-performance CMOS with a high-voltage MOS transistor. A possible choice for the high-voltage device is an n-channel lateral DMOS (NLDMOS) transistor. An advantage of an NLDMOS transistor is that it can be easily integrated within existing technologies without significant process changes. In most cases, though, the drain drift implant must be optimized to meet safe operating area (SOA) and hot carrier (HC) reliability requirements. This paper focuses on understanding anomalous SOA and HC results obtained from an NLDMOS transistor whose drain drift implant dose was varied

Reliability Challenges in Analog and Mixed Signal Technologies

Unique analog product application requirements such as high speed, low noise, low power, high precision and high voltage demand complex analog process technologies. This complexity poses several reliability challenges that are specific to each technology. In this paper some of the key reliability mechanisms in most common analog process technologies are highlighted. To meet broad range of analog IC reliability requirements, in-depth device reliability characterization is essential besides the traditional process reliability qualification.

Electrical characteristics and reliability of extended drain voltage NMOS devices with multi-RESURF junction

The object of this study is to experimentally validate the usefulness of the multi-RESURF and diluted junction methodology to improve the electrical characteristics of lateral extended drain voltage NMOS. Electrical and hot carrier degradation characteristics are discussed. Significant improvement in the device electrical characteristics is shown, while hot carrier degradation was found to be the limiting factor.

1-D and 2-D hot carrier layout optimization of N-LDMOS transistor arrays

Todays power management devices often require operation in the 20-30 V range. These applications often combine a high performance BiCMOS process with a power lateral DMOS (LDMOS) driver. To obtain high drive current density and minimal on-resistance (Rdson), LDMOS devices are often implemented in transistor arrays. Because of the high voltages and currents applied to these LDMOS arrays hot carrier (HC) degradation is a real reliability concern. This paper focuses on improving the HC reliability of N-LDMOS transistor arrays. Layout optimization is emphasized since the LDMOS and Bipolar/CMOS devices share common process steps. This paper differs from previous work in that it discusses for the first time the one- and two-dimensional aspects of LDMOS transistor array layout on HC performance. In addition this paper introduces for the first time a novel LDMOS transistor layout featuring a Drain Ring that dramatically improves the HC performance of these arrays.

Anomalous NMOSFET hot carrier degradation due to trapped positive charge in a DGO CMOS process

It has been reported that MOSFET hot carrier (HC) performance is degraded by back-end-of-line (BEOL) processing steps such as interlayer dielectric film deposition, passivation, and H/sub 2/ annealing. These effects are associated with the incorporation of additional hydrogen at the Si-SiO/sub 2/ interface states to passivate dangling bonds. This paper focuses on an unusual (anomalous) I/sub Dsat/ HC degradation behavior seen on a (DGO) NMOSFET device that was determined to be caused by a dielectric (SiON) contact etch stop process step. This paper presents a novel NMOSFET HC degradation behavior model based on HC injected positive trapped charge that is spatially separated from the normal HC trapped electron charge. This paper shows that this charge separation and positive charge injection creates a secondary impact ionization site that is within the device channel and results in anomalous and accelerated I/sub Dsat/ HC degradation behavior.