Todd Thibeault

Footprint design optimization in SiGe BiCMOS SOI technology

Footprint design in SiGe BiCMOS SOI technology is described in this paper to improve device performance matrix. The safe operating area (SOA) for a SiGe hetero-junction bipolar transistor (HBT) fabricated on silicon on insulator (SOI) is significantly improved as the footprint area increases. The Early voltage for SiGe HBT on SOI at medium-high bias range also increases substantially with footprint area increase. Peak fT and noise figure improves slightly with footprint, and peak fMAX improves slightly then decreases significantly at very large footprint area. A generic tube-area-limited thermal resistance model for BiCMOS devices on SOI is also proposed.

A study of ultra-high performance SiGe HBT devices on SOI

The authors present a study of SiGe HBTs with FT>200GHz on an SOI substrate for the first time. The devices built on SOI exhibit a degradation of approximately 7 Ghz in Ft as compared with bulk devices while Fmax remains near 280 GHz. As expected, Ccs is reduced by ~ 40%. A loss of about 0.75 V in safe operating area is observed for the HBTs built on SOI, but approximately half of this can be regained by allowing the footprint to increase to the original, bulk-silicon HBT footprint by increasing the spacing from the collector to the deep trench isolation.

Developing a High Volume Manufacturing Wet Clean Process to Remove BF2 Implant Induced Molybdenum Contamination

This work details the investigation of potential problems in Complimentary BiCMOS technology, especially PNP transistors arrays. Optical examination of the wafer revealed defects in the P Buried Layer (PBL) areas of the die. Electrical testing correlated these PBL defects to PNP array current leakage. As the PBL module is completed very early on in the process, we devised a shortloop (SL) to reproduce these defects and identify the root cause of current leakage.

A high performance, low complexity 14V Complementary BiCMOS process built on bulk silicon

This paper details a new 14V Complementary BiCMOS (CBiCMOS) addition to the TowerJazz SBC35 family of BiCMOS technologies. The SBC35 family previously supported BVceo values up to 6V. The bipolar architecture is nearly identical with that used in the lower voltage technologies, leveraging 10 years of manufacturing history. The complementary bipolar transistors are paired with 5V CMOS currently available in our SBC35 family. This technology offers high RF performance 14V NPN transistors and PNP transistors with low process complexity. The paper describes a simplified process flow, results of optimization, and a demonstration of the key device performance metrics.