Sergei Kostin

Multiple stuck-at-fault detection theorem

The paper discusses the problem of testing multiple faults in combinational circuits. A definition of a test group is introduced for easier handling of fault masking. Test pair, as a known concept for proving correctness of a line in the circuit is regarded as a special case of the test group. A theorem is proved that if the test group will pass then a particular sub-circuit can be regarded as fault free at any possible combination of stuck-at-faults (SAF) in the circuit. Unlike the traditional approaches, we do not target the faults as test objectives. The goal is to verify the correctness of a part of the circuit. The whole test sequence is presented as a set of test groups where each group has the goal to identify the correctness of a selected part of a circuit.

Hierarchical identification of NBTI-critical gates in nanoscale logic

One of the main reliability concerns in the nanoscale logic is the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). It increases the switching threshold voltage of pMOS transistors and as a result slows down signal propagation along the paths between flip-flops, thus causing functional failures in the circuit. In this paper we propose an approach to identify NBTI-critical gates in nanoscale logic. The method is based on static timing analysis that provides delay critical paths under NBTI-induced delay degradation. An analysis on these critical paths is performed in order to select the set of gates that have the highest influence on circuit aging. These gates are to be hardened against NBTI aging effects guaranteeing correct circuit behavior under the given timing and circuit lifetime constraints. The proposed approach is demonstrated on an industrial ALU circuit design.

Embedded fault diagnosis in digital systems with BIST

This paper presents an optimized fault diagnosing procedure applicable in Built-in Self-Test environments. Instead of the known approach based on a simple bisection of patterns in pseudorandom test sequences, we propose a novel bisection procedure where the diagnostic weight of test patterns is taken into account. Another novelty is the sequential nature of the procedure which allows pruning the search space. Opposite to the classical approach which targets all failing patterns, in the proposed method not all of such patterns are needed to be used for diagnosis. This allows to trade-off the speed of diagnosis with diagnostic resolution. To improve the diagnostic resolution multiple signature analyzers are used. A method is proposed to partition a single signature analyzer into a set of multiple independent analyzers, and the algorithms are given to synthesize an optimal interface between the outputs of the circuit under test and the analyzers. The proposed method is compared with three known fault diagnosis methods: classical Binary Search based on patterns bisection, Doubling and Jumping. Experimental results demonstrate the advantages of the proposed method compared to the previous ones.

Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG

One of the main reliability concerns in the nanoscale logic is the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). It increases the threshold voltage of pMOS transistors, which slows down signal propagation along the paths between flip-flops. As a consequence, NBTI may cause transient faults and, ultimately, permanent circuit functional failure. In this paper, we propose an innovative NBTI mitigation approach by rejuvenation of nanoscale logic along NBTI-critical paths. The method is based on hierarchical NBTI-critical paths identification and rejuvenation stimuli generation using an Evolutionary Algorithm. The rejuvenation stimuli are used to drive to the recovery phase the pMOS transistors that are the most significant for the NBTI-induced path delay. This rejuvenation procedure is to be applied to the circuit as an execution overhead at predefined periods. The proposed approach is aimed at extending the reliable lifetime of nanoelectronics. Experimental results are demonstrated by electrical simulations of an ALU circuit design.

About robustness of test patterns regarding multiple faults

We present a new idea of test groups as a general approach to generate test patterns for multiple stuck-at-faults in combinational circuits. All faults of any multiplicity are assumed present in the circuit and we do not need to enumerate them. Unlike the known approaches, we do not target faults as test objectives. The goal is to verify the correctness of a part of the circuit The final test is presented as a set of test pattern groups where each group has the goal to identify the correctness of a selected part of a circuit. The method facilitates fault diagnosis in the presence of multiple faults. The knowledge about identified correct parts of the circuit allows to extend step by step the core of the circuit proved as correct.

SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic

Accurate prediction of circuit aging is essential to reliable design, in particular for critical applications. Based on intensive HSPICE electrical simulations, we developed a predictive model to compute NBTI-induced path delay degradation at gate-level. The method is based on a static timing analysis that computes path delay under NBTI-induced VTHp (pMOS transistor threshold voltage) degradation. The proposed approach is demonstrated on an industrial ALU circuit design. The obtained results demonstrate a good fitting between the developed model and HSPICE simulations with several orders of magnitude gain in simulation speed.

Identifying NBTI-Critical Paths in Nanoscale Logic

One of the main reliability concerns in the nanoscale logic is the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). It may increase the switching threshold voltage of pMOS transistors and as a result slow down signal propagation along the paths between flip-flops thus causing functional failures in the circuit. In this paper we propose an approach to identify NBTI-critical paths in nanoscale logic that is based on analyzing combination in different degrees of the three parameters: delay-critical paths, gate input signal probability and the gate fan-out degree along the paths. Further the identified NBTI-critical path can be used e.g. for introduction of aging sensors circuitry, rejuvenation stimuli generation, etc. The proposed approach is demonstrated on an industrial ALU circuit design.

Embedded diagnosis in digital systems

A method is proposed for embedded fault diagnosis in digital systems using built-in self-test (BIST) facilities and pseudorandom test sequences. The novelty of the diagnostic strategy is in bisectioning of detected faults instead of traditional bisectioning of patterns in the test sequences. Opposite to the classical approach of fault diagnosis in digital circuits which targets all failing patterns, in the proposed method not all failing patterns are necessarily needed to be fixed for diagnosis. A possibility is analyzed to improve the diagnostic resolution by using multiple signature analyzers. Experimental results demonstrated the feasibility and efficiency of the approach.

Fault Diagnosis in Integrated Circuits with BIST

This paper presents an optimized fault diagnosing procedure applicable in built-in self-test environments. Instead of the known approach based on a simple bisection of patterns in pseudorandom test sequences, we propose a novel bisection procedure where the diagnostic weight of test patterns is taken into account. Another novelty is the sequential nature of the procedure which allows pruning the search space. Opposite to the classical approach which targets all failing patterns, in the proposed method not all failing patterns are needed to be fixed for diagnosis. This allows to tradeoff the speed of diagnosis with diagnostic resolution. The proposed method is compared with three known fault diagnosis methods: classical binary search, doubling and jumping. Experimental results demonstrate the advantages of the proposed method compared to the previous ones.

Block-Level Fault Model-Free Debug and Diagnosis in Digital Systems

The concept of fault model free diagnosis is combined with cause-effect analysis in digital systems represented as networks of functional blocks. We consider the diagnosis as a task to locate a faulty block in the network by using concise block level topological fault dictionaries. The dictionary does not need fault simulation and represents only the connectivity of blocks to observable checkpoints. We define the distance between the entries (codewords) in the dictionary, and make use of these distances to match the observed test responses to the entries of the dictionary. A measure is proposed for evaluating the block-level diagnosability of a given network which can be used for improving the diagnostic resolution. Experimental results provide the data which characterize the proposed measure and show the efficiency of using topological fault dictionaries.