Sergei Devadze

Parallel X-fault simulation with critical path tracing technique

In this paper, a new very fast fault simulation method to handle the X-fault model is proposed. The method is based on a two-phase procedure. In the first phase, a parallel exact critical path fault tracing is used to determine all the detected stuck-at faults in the circuit, and in the second phase a postprocess is launched which will determine the detectability of X-faults.

FPGA-based synthetic instrumentation for board test

This paper studies a new approach for board-level test based on synthesizable embedded instruments implemented on FPGA. This very recent methodology utilizes programmable logic devices (FPGA) that are usually available on modern PCBs to a large extent. The purpose of an embedded instrument is to carry out a vast portion of test application related procedures, perform measurement and configuration of system components thus minimizing the usage of external test equipment. By replacing traditional test and measurement equipment with embedded synthetic instruments it is possible not only to achieve the significant reduction of test costs but also facilitate high-speed and at-speed testing. We detail the motivation and classify the FPGA-based instrumentation into different categories based on the implementation and application domains. Experimental results show the efficiency of this approach.

Effective Scalable IEEE 1687 Instrumentation Network for Fault Management

The infrastructure of IJTAG can be utilized during operation to detect errors and make appropriate fault handling. This article describes an architecture where error latency and automation are important requirements.

Fast extended test access via JTAG and FPGAs

This paper describes a new test access protocol for system-level testing of printed circuit boards for manufacturing defects. We show that the protocol can be based on standard Boundary Scan (BS) instructions and test access mechanism (TAM). It means that the methodology does not require any changes/redesign of hardware and can be immediately implemented in the electronic manufacturing. Our solution needs however a proper software support and availability of programmable devices (FPGAs, CPLDs, etc.) on the board under test. The new technique dramatically extends the applicability of BS testing in the reality of modern complex on-board data transfer buses and protocols. Potentially, it can also increase the speed of in-system programming of flash memories and other tasks that are traditionally performed using BS.

Parallel fault backtracing for calculation of fault coverage

A new improved method for calculation of fault coverage with parallel fault backtracing in combinational circuits is proposed. The method is based on structurally synthesized BDDs (SSBDD) which represent gate-level circuits at higher, macro level where macros represent subnetworks of gates. A topological analysis is carried out to generate an efficient optimized model for backtracing of faults to minimize the repeated calculations because of the reconvergent fanouts. The algorithm is equivalent to exact critical path tracing, however, processing the backtrace in parallel for a group of test patterns. Because of the parallelism, higher abstraction level modeling, and optimization of the topological model, the speed of fault simulation was considerably increased. Compared to the state-of-the-art commercial fault simulators the gain in speed was several times.

Asynchronous Fault Detection in IEEE P1687 Instrument Network

The paper describes asynchronous fault detection in silicon chips with network of embedded instruments based on IEEE P1687 IJTAG. This technique allows faster fault detection and localization by using asynchronous signal propagation from instruments to instrumentation network controller. The additional hardware is described, scenarios of operation including multiple simultaneous fault detection and localization are analysed.

Design, Verification, and Application of IEEE 1687

IEEE 1687 (IJTAG) has been developed to enable flexible and automated access to the increasing number of embedded instruments in todays integrated circuits. These instruments enable efficient post-silicon validation, debugging, wafer sort, package test, burn-in, bring-up and manufacturing test of printed circuit board assemblies, power-on self-test, and in-field test. Current paper presents an overview of challenges as well as selected examples in the following topics around IEEE 1687 networks: (1) design to efficiently access the embedded instruments, (2) verification to ensure correctness, and (3) fault management at functions performed in-field through the products life time.

Fault simulation with parallel exact critical path tracing in multiple core environment

A novel fault simulation method is proposed, based on exact critical path tracing beyond the Fan-out-Free Regions (FFR) throughout the full circuit. The method exploits two types of parallelism: bit-level parallelism for multiple pattern reasoning, and distribution the fault reasoning process between different cores in a multi-core processor environment. To increase the speed and accuracy of fault simulation, compared with previous methods, a mixed level fault reasoning approach is developed, were the fan-out re-convergence is handled on the higher FFR network level, and the fault simulation inside of FFRs relies on the gate-level information. To allow a uniform and seamless fault reasoning, Structurally Synthesized BDDs (SSBDD) are used for modeling on both levels. Experimental research demonstrated very promising results in increasing the speed and scalability of the method.

On-line fault classification and handling in IEEE1687 based fault management system for complex SoCs

Semiconductor products manufactured with latest and emerging processes are increasingly prone to wear out and aging. While the fault occurrence rate in such systems increases, the fault tolerance techniques are becoming even more expensive and one cannot rely on them alone. In addition to mitigating/correcting the faults, the system may systematically monitor, detect, localize, diagnose and classify them (manage faults). As a result of such fault management approach, the system may continue operating and degrade gracefully even in case if some of the systems resources become unusable due to intolerable faults. This works proposes a fault classification and handling methodology that fits to an event-driven on-line fault monitoring, signaling and management architecture based on IEEE1687 IJTAG and suitable for a modern complex SoC with many heterogeneous cores.

Parallel exact critical path tracing fault simulation with reduced memory requirements

A new method based on the critical path tracing is proposed for fault simulation in combinational parts of digital systems. The novelty of the method lays in the possibility to carry out complex computations on sets of faults in parallel simultaneously for many test patterns. A topological analysis is carried out to generate an efficient optimized model for backtracing of faults. Thanks to the parallelism and optimization of the model, the speed of simulation was considerably increased. To overcome the problem of required memory in the case of very large circuits for storing the model, a method of splitting it and the process of parallel reasoning into a number of iterations was proposed. Compared to the state-of-the-art commercial fault simulators the gain in speed was several times.