Darren K. Brock

A superconductor high-resolution ADC

This paper presents the development of an Analog-to-Digital Converter (ADC) based on a low-temperature superconductor (Nb) chip and room-temperature interface modules for applications in digital receivers for communications, radars, and electronic warfare. The ADC design, MATLAB/sup TM/ simulations, and experimental results of single- and two-tone tests are described.

A superconductive flash digitizer with on-chip memory

Recording transient physical phenomena such as short electromagnetic pulses requires a very wide-band digitizer. We have successfully designed, fabricated, and tested a superconductive flash digitizer circuit using Nb trilayer technology. The digitizer consists of a 6-bit flash analog-to-digital converter (ADC), a set of on-chip switches to start and stop data acquisition, and a bank of acquisition shift-registers for on-chip memory. A 5-MHz clock reads the data out to room-temperature electronics for analysis. We have used this digitizer to acquire multi-GHz sine waves. We have also recorded the details of short single pulses containing both a short rise time (/spl sim/100 ps) and structure with greater than a 10 GHz instantaneous bandwidth.

High resolution ADC using phase modulation-demodulation architecture

We report successful demonstration of a fully operational integrated superconducting ADC system based on a phase modulation/demodulation architecture. It consists of a high-resolution ADC chip with a multiple-channel race arbiter and integrated bit-pipelined decimation filter, an interface electronics block converting the ADC output to standard ECL form at sampling rates up to 200 MHz, and a computerized test station performing data acquisition, processing and display in real time. We have demonstrated a fully functional 14-bit ADC chip with 2-channel race arbiter and 16-bit decimation filter with 1:64 decimation ratio operating at 11.2 GS/s. By using additional decimation filtering of the ADC output at room temperature we demonstrated its dynamic programmability and resolution-bandwidth tradeoff. The measured ADC performance (on effective bits) was competitive with the best semiconductor high-resolution ADCs.

Retargeting RSFQ cells to a submicron fabrication process

There is a desire to move current state-of-the-art niobium Josephson IC fabrication processes (/spl sim/3 /spl mu/m) to smaller sub-micron linewidths in order to realize a decrease in gate size and increase in both speed and packing density. However, cost and time dictates that a way be found to reuse the existing RSFQ gate/cell development that has been done at the 3-/spl mu/m level. Cell retargeting is the process of migrating existing designs to a new technology, with the effort focused on the maximum reuse of existing material. We have investigated a number of issues critical to this process, including both the physical and electrical aspects. Comments are made on methodologies for RSFQ cell retargeting with respect to existing reduced-linewidth JJ fabrication processes. Experimental demonstrations are shown for retargeted RSFQ static digital frequency dividers (toggle flip-flops) operating at 220 GHz, 240 GHz, and 395 GHz.

Can RSFQ logic circuits be scaled to deep submicron junctions

Scaling of niobium RSFQ integrated circuit technology to deep submicron dimensions (linewidths of 300 nm or less) should permit increased clock rate (up to 250 GHz) and increased areal density of Josephson junctions (up to 1 million junctions/cm/sup 2/), without the need for external shunt resistors. It is shown how existing circuit layouts can be scaled down to these dimensions, while maintaining the precise timing essential for correct operation. Additional issues related to the practical realization of such circuits are discussed, including effects of self-heating and models for the generation and propagation of sub-ps single-flux-quantum pulses.

Toward a systematic design methodology for large multigigahertz rapid single flux quantum circuits

Rapid single flux quantum (RSFQ) digital circuits have reached the level of medium- to large-scale of integration. At this level, existing design methodologies, developed specifically for RSFQ circuits, have become computationally inefficient. Applying mature semiconductor methodologies to the design of RSFQ circuits, one encounters substantial difficulties originating from the differences between both technologies. In this paper, a new design methodology aimed at large-scale RSFQ circuits is proposed. This methodology is based on a semiconductor semicustom design approach. An established design methodology for small-stale RSFQ digital circuits, based on circuit (junction-level) simulation and device parameter optimization, is used for the design of basic RSFQ cells. A library composed of about 20 basic RSFQ cells has been developed based on this approach. A novel design methodology for large-scale circuits, presented in this paper, is based on logic (gate-level) simulation and timing optimization. This methodology has been implemented around the Cadence integrated design environment and used successfully at the University of Rochester for the design of two large-scale digital circuits.

A Cadence-based design environment for single flux quantum circuits

The semiconductor industry standard computer-aided-design (CAD) tool Cadence has been calibrated for a 3 /spl mu/m Niobium technology in order to design and build superconductive single flux quantum (SFQ) circuits. The top-down design methodology includes Verilog functional simulation, schematic capture, graphic layout, functional verification, design rule checking, electrical rule checking, and layout-vs.-schematic verification. This design framework has been used successfully at the University of Rochester in designing more than 15 elementary SFQ cells and three large scale digital and mixed-signal SFQ circuits, demonstrating significant improvement in both design efficiency and accuracy.

Pipelined DC-powered SFQ RAM

We present the design and test results of components for a superconductor Cryogenic Random Access Memory (CRAM). The 16-Kb RAM design consists of four 4-Kb sub-arrays (blocks) with a 400 ps access time (latency) and a 100 ps cycle time (throughput). Each 4-Kb RAM block comprises a row-accessed 32/spl times/128 memory cell array, bipolar line drivers, row decoders, and column sense circuits. The implementation of specially designed distributed Josephson junctions in the sensing circuits reduces the overall size of the blocks and allows the use of smaller dc control currents.

Integrated millimeter/submillimeter superconducting digital spectrometer

Compact mm/submm integrated spectrometers are required for radio-astronomical research, remote monitoring of the Earth atmosphere and environmental monitoring for hazardous materials of chemical and biological origin. Assembled on a multi-chip module the all superconducting integrated spectrometer offers integration of thin film analog components such as a mixer, superconducting local oscillator and an intermediate frequency SQUID amplifier together with superconducting digital circuitry. A Rapid Single Flux Quantum (RSFQ) 128-bit autocorrelator formed by 16-bit autocorrelator and a 112-bit programmable shift register that adjusts the data delay in increments of 16, is used for digitizing of the down converted signals and real-time digital processing. Experimental results showing both operation of components and the way to their successful integration are presented.

Design and testing of QOS comparators for an RSFQ based analog to digital converter

Successful utilization of the quasi one-junction SQUID (QOS) as a signal comparator for analog-to-digital conversion (ADC) has been demonstrated by several groups, This idea is extended to show how similar comparators can be integrated into an all rapid single flux quantum (RSFQ) digital architecture. Comparators are interrogated by SFQ sampling pulses and in turn give output according to the RSFQ convention. One- and two-bit ADCs have been simulated, fabricated and tested at low speed. Total performance of these devices is estimated within the framework of a multiple bit parallel flash ADC architecture.<<ETX>>