Serguei Okhonin

A SOI capacitor-less 1T-DRAM concept

A simple 1T DRAM cell concept is proposed for the first time. It exploits the body charging of PD SOI devices to store the information. This cell is at least two times smaller in area than the conventional 1T/1C DRAM cell and does not require the integration of a storage capacitor. This concept should allow the manufacture of low cost DRAMs and eDRAMs for 100 and sub 100 nm generations.

A simple 1-transistor capacitor-less memory cell for high performance embedded DRAMs

A new compact memory architecture is proposed for embedded dynamic random access memory (eDRAM) cells. By exploiting the floating body effect of partially depleted silicon on insulator (SOI) devices, a one-transistor memory cell can be integrated in a pure logic SOI technology without adding any process step. The data retention, device operation principles and reliability make it ideal for high performance eDRAM applications while reducing the cell area by a factor of two.

A leakage current model for SOI based floating body memory that includes the Poole-Frenkel effect

The leakage current of SOI based Floating Body Memory (FBM) has been modeled. The model takes into account oxide/SOI interface traps (Dit) and Electric Field Enhanced (EFE) generation of electron hole pairs (EHPs) from trap states via the Poole-Frenkel Effect (PFE). This model has been used to improve the retention time of Z-RAM by a reduction of both Dit and electric field. It can also be extended to SOI based low power devices.

Capacitorless 1T DRAM sensing scheme with automatic reference generation

To perform a current sensing in capacitorless 1-transistor (1T) DRAMs on SOI, we have developed a sensing scheme with automatic reference generation. The reference current is generated by an adjustable current source. The electrical calibration of the reference current source is performed using a digital-to-analog converter and a successive approximations algorithm. By setting the reference just below the current of the data state 1, the data retention time in the holding mode is maximized. The proposed scheme is evaluated in a 2-kb test chip implemented in a 1-/spl mu/m partially depleted (PD) SOI process. The measured retention time under holding conditions is higher than 1s. In the continuous read mode, a few hundreds of the read cycles can be performed without a refresh operation. The test chip measures an access time of 25 ns with a read cycle time of 70 ns.

SOI capacitor-less 1-transistor DRAM sensing scheme with automatic reference generation

Recently, the new concept of the capacitor-less 1T DRAM cell has been developed. The memory cell (MC) using a single transistor on SOI exploits the Floating Body (FB) effect of partially depleted (PD) SOI devices. The memory state can be read through the drain current of the storage transistors, i.e. I/sub 0/ and I/sub 1/ respectively. To read the information stored in a 1T DRAM cell, the current of the selected MC is compared to I/sub ref/ . In this paper, we propose a sensing method with automatic reference generation for SOI capacitor-less 1T DRAM. An adjustable current source is implemented as reference current source in order to sense the MC state. A digital-to-analog converter (DAC) and a successive approximation algorithm perform the calibration of I/sub ref/.

Zero capacitor embedded memory technology for system on chip

By harnessing the floating body (FB) effect of silicon on insulator devices, the authors introduced a true capacitor-less, single transistor DRAM - named Z-RAMtrade (zero capacitance DRAM) - which is capable of doubling memory density when compared to existing embedded DRAM technology (and achieving five times the density of current embedded SRAM), yet requires no exotic materials, no extra mask steps and no new physics. As no capacitor is required, the Z-RAM cell can readily be scaled as far as the transistor. The technologys bit-cell scalability was demonstrated at the 45nm node. It is easily envisaged that Z-RAM technology will scale well to at least the 22nm process node and ISi has already measured suitable characteristics in the FinFET transistors that may well be used at that time

A CMOS compatible low power ultra dense capacitor less SOI RAM

This paper presents low power writing mechanisms for the ultra dense capacitor less RAM cell on SOI (silicon-on-insulator). By exploiting band to band tunneling and negative voltages, no current flows in the cell during writing and large programming windows is obtained. First results on data disturb is presented. evidence of a charge pumping related related gate disturb is shown.