Pierre Fazan

Inversion charge linearization in MOSFET modeling and rigorous derivation of the EKV compact model

Abstract In this paper, the implications of inversion charge linearization in compact MOS transistor modeling are discussed. The charge-sheet model provides the basic relation among inversion charge and applied potentials, via the implicit surface potential. A rigorous derivation of simpler relations among inversion charge and applied external potentials is provided, using the technique of inversion charge linearization versus surface potential. The new concept of the pinch-off surface potential and a new definition of the inversion charge linearization factor are introduced. In particular, we show that the EKV charge-based model can be considered as an approximation to the more general approach presented here. An improvement to the EKV charge-based model is proposed in the form of a more accurate charge–voltage relationship. This model is analyzed in detail and shows an excellent agreement with the charge sheet model. The normalization of voltages, current and charges, as motivated by the inversion charge linearization, results in a major simplification in compact modeling in static as well as non-quasi-static derivations.

A simple 1-transistor capacitor-less memory cell for high performance embedded DRAMs

A new compact memory architecture is proposed for embedded dynamic random access memory (eDRAM) cells. By exploiting the floating body effect of partially depleted silicon on insulator (SOI) devices, a one-transistor memory cell can be integrated in a pure logic SOI technology without adding any process step. The data retention, device operation principles and reliability make it ideal for high performance eDRAM applications while reducing the cell area by a factor of two.

Highly manufacturable capacitor-less 1T-DRAM concept

We introduce a new cell architecture for Dynamic Random Access Memory (DRAM) and embedded DRAM applications. By exploiting the Floating Body characteristics of partially depleted silicon on insulator (SOI) transistors, a capacitor-less DRAM cell structure can store and amplify the stored signal by using only a single transistor. Such a DRAM cell has a footprint two times smaller than that of standard DRAM cells and can be integrated in any CMOS process.

Accounting for quantum effects and polysilicon depletion from weak to strong inversion in a charge-based design-oriented MOSFET model

This paper presents a simple, physics-based, and continuous model for the quantum effects and polydepletion in deep-submicrometer MOSFETs with very thin gate oxide thicknesses. This analytical design-oriented MOSFET model correctly predicts inversion and depletion charges, transcapacitances, and drain current, from weak to strong inversion and from nonsaturation to saturation. One single additional parameter is used for polysilicon doping concentration, while the quantum correction does not introduce any new parameter. Comparison to experimental data of deep-submicrometer technologies is provided, showing accurate fits both for I-V and C-V data. The model offers simple relationships among effective electrical parameters and physical device parameters, providing insight into the physical phenomena. This new model thereby supports device engineering, analog circuit design practice, as well as efficient circuit simulation.

ELECTRICAL MODELING OF A PRESSURE SENSOR MOSFET

Abstract This paper presents a simple and efficient analytical model of a MOS transistor-based pressure sensor. Starting from basic MOS equations, we derive a general relation between the gate transconductance and an equivalent gate capacitance that varies with pressure and whose definition represents a major improvement. Furthermore, such relation was found to be nearly independent of the MOS parameters and hence of the fabrication technology, in contrast with previous works. Results obtained with the present model are compared to two-dimensional (2D) simulations and model limitations are discussed in details.

Low-pressure chemical vapour deposition of nanograin polysilicon ultra-thin films

With this work we have assessed the minimum thickness and grain size realizable for a polysilicon (poly-Si) layer deposited with a low-pressure chemical vapour deposition technique. Three different approaches using pure silane in a standard horizontal reactor have been evaluated: (i) a direct poly-Si deposition, (ii) a hemispherical silicon grain deposition and (iii) an amorphous silicon (a-Si) deposition followed by crystallization thermal annealing. It has been demonstrated that the a-Si/crystallization process seems to be the best candidate for the deposition of ultra-thin poly-Si films. However, it involves process innovation in both the nucleation and annealing phases. With this method we have succeeded in the deposition of uniform 6 nm poly-Si layers with grain sizes around 10-20 nm.

Modeling the polarization in ferroelectric materials: A novel analytical approach

Abstract We propose for the first time a fully analytical formulation of the polarization in ferroelectric materials that takes into account history effects. Our approach is based on the Preisach theory of the hysteresis loops. A symmetric exponential decay distribution of the dipoles thresholds has been introduced. Consequently, an exact analytical and continuous solution of the polarization could be derived, taking the electric field history into consideration. Experimental data on PZT capacitors show relevant agreement with the model for both saturated and minor loops. This confirms the validity of this approach, which consequently represents a very interesting candidate for efficient ferroelectric compact models to be used either in memory or in analog design applications.

Ultra‐High Capacitance Nitride Films Utilizing Surface Passivation on Rugged Polysilicon

This paper describes high performance capacitors formed with silicon nitride dielectrics which meet the requirements for advanced stacked storage structures in 64 Mbit DRAM and beyond. A novel combination of a rugged polysilicon bottom electrode and an ultra-thin nitride deposited with a surface passivation technique was used. We show that these structures can achieve up to 12 fF/μm 2 for 3.3 V applications. We demonstrate that 4-nm thick nitride films which feature low leakage, high capacitance, and excellent reliability can be fabricated

Nitridation of thin SiO2 films in N2 and NH3 plasmas

Abstract A low-temperature (700°C) plasma-enhanced nitridation process which improves the dielectric breakdown of thin silicon dioxide (SiO2) layers is presented. It uses a new, production compatible, parallel plate plasma reactor working at low RF frequencies. Nitrided oxides produce less charge trapping under high field stress, higher breakdown charge and a tighter distribution of breakdown fields than pure SiO2. More nitrogen is incorporated in films treated in a NH3 plasma than in a N2 plasma. However, the latter present better electrical properties.

Two-band tunneling currents in metal-oxide-semiconductor capacitors at the transition from direct to Fowler–Nordheim tunneling regime

The conduction and valence band tunneling currents in ultrathin SiO2 films are studied. The slopes of the current–voltage characteristic agree well with the simulations performed. Conduction band current oscillations due to interference of the electrons from the inversion channel at the oxide/gate interface are observed. The shape of the slope of the valence band current in Fowler–Nordheim regime can be explained by the interference of the valence band electron wave at the oxide/gate interface.