Mikhail Nagoga

A SOI capacitor-less 1T-DRAM concept

A simple 1T DRAM cell concept is proposed for the first time. It exploits the body charging of PD SOI devices to store the information. This cell is at least two times smaller in area than the conventional 1T/1C DRAM cell and does not require the integration of a storage capacitor. This concept should allow the manufacture of low cost DRAMs and eDRAMs for 100 and sub 100 nm generations.

A simple 1-transistor capacitor-less memory cell for high performance embedded DRAMs

A new compact memory architecture is proposed for embedded dynamic random access memory (eDRAM) cells. By exploiting the floating body effect of partially depleted silicon on insulator (SOI) devices, a one-transistor memory cell can be integrated in a pure logic SOI technology without adding any process step. The data retention, device operation principles and reliability make it ideal for high performance eDRAM applications while reducing the cell area by a factor of two.

A leakage current model for SOI based floating body memory that includes the Poole-Frenkel effect

The leakage current of SOI based Floating Body Memory (FBM) has been modeled. The model takes into account oxide/SOI interface traps (Dit) and Electric Field Enhanced (EFE) generation of electron hole pairs (EHPs) from trap states via the Poole-Frenkel Effect (PFE). This model has been used to improve the retention time of Z-RAM by a reduction of both Dit and electric field. It can also be extended to SOI based low power devices.

Highly manufacturable capacitor-less 1T-DRAM concept

We introduce a new cell architecture for Dynamic Random Access Memory (DRAM) and embedded DRAM applications. By exploiting the Floating Body characteristics of partially depleted silicon on insulator (SOI) transistors, a capacitor-less DRAM cell structure can store and amplify the stored signal by using only a single transistor. Such a DRAM cell has a footprint two times smaller than that of standard DRAM cells and can be integrated in any CMOS process.

Transient effects in PD SOI NMOSFETs

We investigated the transients in 0.25 μm PD SOI devices. A good agreement between experimental and simulation results has been observed. The exponential dependence of the switch-on transient time on the reciprocal drain voltage for both p- and n-channel devices is explained by the predominance of the impact ionisation mechanism.