Seth J. Wilk

SOI MESFETs Fabricated Using Fully Depleted CMOS Technologies

Ultrathin channel metal-semiconductor field-effect-transistors (MESFETs) have been fabricated using fully depleted silicon-on-insulator CMOS foundries with no changes to the process flow. The Schottky gate of the MESFET is formed from a metal silicide that consumes most of the thin ( < 50 nm) FD-SOI channel and fully depletes the remaining underlying silicon. Therefore, unlike partially depleted SOI MESFETs with a thicker silicon layer ( ~ 200 nm), the conducting channel of the FD-SOI MESFET cannot be formed directly under the Schottky gate. Instead, current flow in the FD-SOI MESFET is confined between islands of silicide that deplete the conducting channel in a lateral direction. The FD-SOI MESFETs operate as depletion mode devices with a threshold voltage that can be adjusted by varying the separation between the silicide islands. Both n- and p-channel devices can be realized using the same gate material on a common FD-SOI substrate.

Teflon™-coated silicon apertures for supported lipid bilayer membranes

We present a method for microfabricating apertures in a silicon substrate using well-known cleanroom technologies resulting in highly reproducible giga-seal resistance bilayer formations. Using a plasma etcher, 150μm apertures have been etched through a silicon wafer. Teflon™ has been chemically vapor deposited so that the surface resembles bulk Teflon and is hydrophobic. After fabrication, reproducible high resistance bilayers were formed and characteristic measurements of a self-inserted single OmpF porin ion channel protein were made.

Scaling SOI MESFETs to 150-nm CMOS Technologies

Metal-semiconductor field-effect transistors (MESFETs) have been fabricated using a 150-nm partially depleted silicon-on-insulator complementary metal-oxide-semiconductor (CMOS) technology. Minimum gate lengths of 150 nm have been achieved, which represents a significant reduction compared with an earlier demonstration using a 350-nm CMOS technology. The scaled MESFETs with Lg = 150 nm have a current drive that exceeds 200 mA/mm with a peak fT >; 35 GHz. This is considerably higher than the Lg = 400 nm MESFET with a current drive of ~70 mA/mm and a peak fT = 10.6 GHz, which was possible with the earlier generation. However, short-channel effects become significant for Lg <; 400 nm, resulting in an optimum MESFET gate length for this technology in the range of 200-300 nm.

Fabrication of Cylindrical Nanopores and Nanopore Arrays in Silicon-On-Insulator Substrates

Electron-beam lithography and reactive ion etching were used to process silicon-on-insulator substrates for the fabrication of single cylindrical high-aspect-ratio solid-state nanopores and high-packing-density nanopore arrays. Minimum pore diameters of 40 nm were readily achieved with a high yield. The electrolyte concentration dependence of ion transport through single nanopores was measured for pores with diameters ranging from 40 to 140 nm. Measured single-nanopore conductances in high salt concentrations were compared to a simple model using a cylindrical resistance path and bulk solution conductivity. Electrochemical impedance spectroscopy was used to study the ac response of the device.

32 dBm Power Amplifier on 45 nm SOI CMOS

A silicon metal-semiconductor-field-effect-transistor (MESFET) power amplifier operating at 900 MHz fabricated on a 45 nm silicon-on-insulator CMOS process with no changes to the process flow is presented. The soft breakdown of the MESFET is 20 times that of the MOSFET and allowed a single transistor amplifier based on Class A bias conditions to operate at up to 32 dBm output power with an 8 V drain bias. The amplifier had a peak power added efficiency of 37.6%, gain of 11.1 dB, OIP3 of 39.3 dBm and 1 dB compression point at an output power of 31.6 dBm. The device required only 0.125 mm 2 of active area. Additionally, the depletion mode operation of the MESFET enables a simple input bias approach using an inductor to ground at the gate of the device.

Formation of nanopores in suspended lipid bilayers using quantum dots

In this work, nanopores are formed in lipid (DOPC:DOPE) membranes suspended across 150 micron apertures by oligomeric aggregation of 12 nm diameter CdSe quantum dots. The bilayer and quantum dot nanopores are simultaneously characterized by low noise electrical current monitoring and epifluorescence microscopy. Suspended lipid bilayers form high resistance gigaseals (>10 GOhm) that serve as barriers to the migration of charged ions and particles. Oligomeric aggregation of quantum dots is observed on the surface of the suspended lipid bilayer in the presence of charge stabilized quantum dot suspensions, The aggregate forms a nanometer scale pore (~2 nm in diameter) in the bilayer resulting in non-quantal ion current bursts. Migration of net neutral Rhodamine B dye (1.6 nm molecular diameter) across the bilayer is measured only in the presence of the aggregates. Potential applications for the non-lithographic fabrication of bilayer nanopores include biochemical detection, DNA sequencing, or cellular drug delivery.

An integrated MESFET voltage follower LDO for high power and PSR RF and analog applications

A CMOS low dropout linear regulator (LDO) with a MESFET based follower output stage was designed and fabricated on a commercial 45nm SOI CMOS technology. The proposed LDO demonstrates a dropout voltage of <;170mV at 1A load current while occupying 0.245mm2 of die area. The approach includes a novel depletion mode n-channel MESFET in a low output impedance source follower configuration. This enables the LDO to achieve stable operation under all line and load conditions without the need for generating higher internal voltage rails or external compensation. The compact structure and its inherent stability make it ideal for high powered analog, mixed signal and RF system-on-chip applications that require high PSR under different loading conditions.

Demonstration of Coulter counting through a cylindrical solid state nanopore

The technique known as a Coulter counting, or resistive-pulse sensing, can be used to measure the size of a nanoscale analyte as it passes through a fluidic constriction separating two reservoirs. We have developed a fabrication procedure capable of reproducibly manufacturing cylindrical nanopores with diameters as small as 20 nm using a silicon-on-insulator substrate and electron beam lithography. The ionic conductance of these nanopores was measured across six orders of magnitude in electrolyte concentration. Polystyrene nanoparticles were then passed through the cylindrical pores while monitoring the current that flowed due to a constant bias voltage. Current pulses due to the passage of individual nanoparticles of various dimensions through a nanopore were observed and compared to theory.

Characterization and modeling of enhanced voltage RF MESFETs on 45nm CMOS for RF applications

Enhanced voltage silicon metal-semiconductor-field-effect-transistors (MESFETs) have been fabricated on a 45 nm SOI CMOS technology with no process changes. MESFETs scaled to Lg = 184 nm were fabricated and show a peak fT of 35 GHz, current drive of 112 mA/mm and breakdown voltages exceeding 4.5 V whereas the nominal CMOS voltage was less than 1V on the same process. The devices were characterized from DC to 40 GHz and an industry standard TOM3 model has been developed describing their operation. A board level Class AB power amplifier operating at 433 MHz was designed, fabricated and measured to have a peak output power of 17 dBm and peak PAE of 42.5%. The supply voltage of the PA was more than twice the breakdown voltage of corresponding CMOS on the same semiconductor process. The measured PA results were used to validate the model across different bias and input power level conditions.

A capacitor-free LDO using a FD Si-MESFET pass transistor

The rapid growth in portable electronics has driven the market for ultra low dropout regulators (LDOs) that are more power efficient and lead to longer battery lifetime. Over the years various topologies based on P- or N-channel pass transistors have been introduced to meet these demands. For each of these implementations, the LDO has had a significant disadvantage whether it is stability issues and lower current drive associated with P-channel devices or the need for a charge pump to overcome the threshold voltage drop for enhancement mode N-channel devices. This paper presents a design methodology for an LDO that features a depletion-mode N-MESFET as the pass device that combines the advantages of both P and N devices allowing for ultra low dropout voltage and minimum layout area. The LDO also saves board space and simplifies design by achieving stability across all load and temperature conditions without the need of an output capacitor.