William Lepkowski

SOI MESFETs Fabricated Using Fully Depleted CMOS Technologies

Ultrathin channel metal-semiconductor field-effect-transistors (MESFETs) have been fabricated using fully depleted silicon-on-insulator CMOS foundries with no changes to the process flow. The Schottky gate of the MESFET is formed from a metal silicide that consumes most of the thin ( < 50 nm) FD-SOI channel and fully depletes the remaining underlying silicon. Therefore, unlike partially depleted SOI MESFETs with a thicker silicon layer ( ~ 200 nm), the conducting channel of the FD-SOI MESFET cannot be formed directly under the Schottky gate. Instead, current flow in the FD-SOI MESFET is confined between islands of silicide that deplete the conducting channel in a lateral direction. The FD-SOI MESFETs operate as depletion mode devices with a threshold voltage that can be adjusted by varying the separation between the silicide islands. Both n- and p-channel devices can be realized using the same gate material on a common FD-SOI substrate.

Scaling SOI MESFETs to 150-nm CMOS Technologies

Metal-semiconductor field-effect transistors (MESFETs) have been fabricated using a 150-nm partially depleted silicon-on-insulator complementary metal-oxide-semiconductor (CMOS) technology. Minimum gate lengths of 150 nm have been achieved, which represents a significant reduction compared with an earlier demonstration using a 350-nm CMOS technology. The scaled MESFETs with Lg = 150 nm have a current drive that exceeds 200 mA/mm with a peak fT >; 35 GHz. This is considerably higher than the Lg = 400 nm MESFET with a current drive of ~70 mA/mm and a peak fT = 10.6 GHz, which was possible with the earlier generation. However, short-channel effects become significant for Lg <; 400 nm, resulting in an optimum MESFET gate length for this technology in the range of 200-300 nm.

32 dBm Power Amplifier on 45 nm SOI CMOS

A silicon metal-semiconductor-field-effect-transistor (MESFET) power amplifier operating at 900 MHz fabricated on a 45 nm silicon-on-insulator CMOS process with no changes to the process flow is presented. The soft breakdown of the MESFET is 20 times that of the MOSFET and allowed a single transistor amplifier based on Class A bias conditions to operate at up to 32 dBm output power with an 8 V drain bias. The amplifier had a peak power added efficiency of 37.6%, gain of 11.1 dB, OIP3 of 39.3 dBm and 1 dB compression point at an output power of 31.6 dBm. The device required only 0.125 mm 2 of active area. Additionally, the depletion mode operation of the MESFET enables a simple input bias approach using an inductor to ground at the gate of the device.

An integrated MESFET voltage follower LDO for high power and PSR RF and analog applications

A CMOS low dropout linear regulator (LDO) with a MESFET based follower output stage was designed and fabricated on a commercial 45nm SOI CMOS technology. The proposed LDO demonstrates a dropout voltage of <;170mV at 1A load current while occupying 0.245mm2 of die area. The approach includes a novel depletion mode n-channel MESFET in a low output impedance source follower configuration. This enables the LDO to achieve stable operation under all line and load conditions without the need for generating higher internal voltage rails or external compensation. The compact structure and its inherent stability make it ideal for high powered analog, mixed signal and RF system-on-chip applications that require high PSR under different loading conditions.

Compact modeling of a PD SOI MESFET for wide temperature designs

A compact model for the partially depleted (PD) silicon-on-insulator (SOI) metal semiconductor field effect transistor (MESFET) is presented. The absence of a gate-oxide makes the SOI MESFET extremely robust, able to withstand high voltages, and useful for extreme environment electronics. These devices have been fabricated using a standard SOI CMOS process. In contrast to SOI MOSFETs and GaAs MESFETs, the source-substrate voltage has a significant impact on the channel current. In this work a model has been developed that includes the effect of the buried oxide on the performance of the MESFET. The model has been verified for a wide temperature range of -180 to 150^oC. A behavioral model has been included to model the breakdown voltage. The core DC and RF models have been adapted from the commercially available Triquints Own Model (TOM3) MESFET model. Building from the TOM3 model, a measurement-based approach is used to develop a four-terminal compact model using Verilog-A. The charge-based approach, using S-parameter measurements was used to develop the capacitance model. We also present a voltage reference circuit using two MESFET transistors to verify the model and explore wide temperature range circuit applications.

Characterization and modeling of enhanced voltage RF MESFETs on 45nm CMOS for RF applications

Enhanced voltage silicon metal-semiconductor-field-effect-transistors (MESFETs) have been fabricated on a 45 nm SOI CMOS technology with no process changes. MESFETs scaled to Lg = 184 nm were fabricated and show a peak fT of 35 GHz, current drive of 112 mA/mm and breakdown voltages exceeding 4.5 V whereas the nominal CMOS voltage was less than 1V on the same process. The devices were characterized from DC to 40 GHz and an industry standard TOM3 model has been developed describing their operation. A board level Class AB power amplifier operating at 433 MHz was designed, fabricated and measured to have a peak output power of 17 dBm and peak PAE of 42.5%. The supply voltage of the PA was more than twice the breakdown voltage of corresponding CMOS on the same semiconductor process. The measured PA results were used to validate the model across different bias and input power level conditions.

A capacitor-free LDO using a FD Si-MESFET pass transistor

The rapid growth in portable electronics has driven the market for ultra low dropout regulators (LDOs) that are more power efficient and lead to longer battery lifetime. Over the years various topologies based on P- or N-channel pass transistors have been introduced to meet these demands. For each of these implementations, the LDO has had a significant disadvantage whether it is stability issues and lower current drive associated with P-channel devices or the need for a charge pump to overcome the threshold voltage drop for enhancement mode N-channel devices. This paper presents a design methodology for an LDO that features a depletion-mode N-MESFET as the pass device that combines the advantages of both P and N devices allowing for ultra low dropout voltage and minimum layout area. The LDO also saves board space and simplifies design by achieving stability across all load and temperature conditions without the need of an output capacitor.

40V MESFETs fabricated on 32nm SOI CMOS

This article describes 40V N-channel MESFETs fabricated at a commercial 32nm SOI CMOS foundry without changing any of the process flow or including additional mask steps. The 32nm technology node is the most advanced technology node to date for MESFET fabrication and builds upon previous work completed at other process nodes. High voltage MESFETs were measured with current drives of 110mA/mm. The devices are suitable for RF development and have peak cut-off frequency, fT, of 30.5GHz and maximum oscillation frequency, fmax, of 34.5GHz.

High voltage SOI MESFETs at the 45nm technology node

Enhanced voltage SOI MESFETs have been demonstrated on a highly scaled CMOS process. Their DC and RF performance along with reproducibility suggests that they would be ideal in a variety of analog and PA applications. Also, since they can be fabricated alongside the 45nm CMOS [4], they appear suitable for system-on-chip applications as an interface between high voltage external devices and the low voltage CMOS. While these initial results are encouraging, new MESFET geometries and structures have been taped out to further enhance the breakdown voltage. Lastly, with continued layout optimization it is expected that the variance between devices will be reduced.

Wideband class AB RF power amplifier using CMOS compatible SOI-MESFET device on 150nm technology

In this paper, a wideband class AB power amplifier (PA) centered around 400MHz with 200MHz bandwidth, featuring a CMOS compatible MESFET on a 150 nm SOI technology is presented. It is the first board level demonstration of a SOI-MESFET based RF PA. SOI-MESFETs are an ideal candidate for integrated RF PAs due to their enhanced voltage capability and high cut-off frequency. The MESFET used in this design had a peak fT of 22 GHz and a soft-breakdown of 5V; however, different MESFETs on the same process have achieved a breakdown voltage up to 12V and peak fT up to 40 GHz. Comparatively, the standard CMOS transistors on this process have a maximum steady-state voltage of 1.95V. A peak PAE of 48% has been measured while delivering 17dBm of power to a 50 load. Also, a calibrated TOM3 model has been developed for simulation purposes.