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Dive into the research topics where Seung-Bae Jeon is active.

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Featured researches published by Seung-Bae Jeon.


ACS Nano | 2016

Triboelectric Nanogenerator Based on the Internal Motion of Powder with a Package Structure Design

Daewon Kim; Yura Oh; Byeong Woon Hwang; Seung-Bae Jeon; Sang-Jae Park; Yang-Kyu Choi

Harvesting the ambient mechanical energy that is abundant in the living environment is a green technology which can allow us to obtain an eco-friendly and sustainable form of energy. Here, we report a powder-based triboelectric nanogenerator (P-TENG) using polytetrafluoroethylene powder as a freestanding triboelectric layer. By employing powder, which has fluid-like characteristics, the device is able to harvest random vibrational energy from all directions and can be fabricated regardless of the size or shape of its container. Notably, this device shows excellent durability against mechanical friction and immunity against humidity. It is also capable of powering 240 green LEDs and charging a commercial energy-harvesting battery. The P-TENG is expected to be applicable as an energy harvester in self-powered systems for the upcoming Internet-of-Things era.


Nano Letters | 2015

Vertically Integrated Multiple Nanowire Field Effect Transistor

Byung-Hyun Lee; Min-Ho Kang; Dae-Chul Ahn; Jun-Young Park; Tewook Bang; Seung-Bae Jeon; Jae Hur; Dongil Lee; Yang-Kyu Choi

A vertically integrated multiple channel-based field-effect transistor (FET) with the highest number of nanowires reported ever is demonstrated on a bulk silicon substrate without use of wet etching. The driving current is increased by 5-fold due to the inherent vertically stacked five-level nanowires, thus showing good feasibility of three-dimensional integration-based high performance transistor. The developed fabrication process, which is simple and reproducible, is used to create multiple stiction-free and uniformly sized nanowires with the aid of the one-route all-dry etching process (ORADEP). Furthermore, the proposed FET is revamped to create nonvolatile memory with the adoption of a charge trapping layer for enhanced practicality. Thus, this research suggests an ultimate design for the end-of-the-roadmap devices to overcome the limits of scaling.


Scientific Reports | 2015

Floating Oscillator-Embedded Triboelectric Generator for Versatile Mechanical Energy Harvesting.

Myeong-Lok Seol; Jin-Woo Han; Seung-Bae Jeon; M. Meyyappan; Yang-Kyu Choi

A versatile vibration energy harvesting platform based on a triboelectricity is proposed and analyzed. External mechanical vibration repeats an oscillating motion of a polymer-coated metal oscillator floating inside a surrounding tube. Continuous sidewall friction at the contact interface of the oscillator induces current between the inner oscillator electrode and the outer tube electrode to convert mechanical vibrations into electrical energy. The floating oscillator-embedded triboelectric generator (FO-TEG) is applicable for both impulse excitation and sinusoidal vibration which universally exist in usual environment. For the impulse excitation, the generated current sustains and slowly decays by the residual oscillation of the floating oscillator. For the sinusoidal vibration, the output energy can be maximized by resonance oscillation. The operating frequency range can be simply optimized with high degree of freedom to satisfy various application requirements. In addition, the excellent immunity against ambient humidity is experimentally demonstrated, which stems from the inherently packaged structure of FO-TEG. The prototype device provides a peak-to-peak open-circuit voltage of 157 V and instantaneous short-circuit current of 4.6 μA, within sub-10 Hz of operating frequency. To visually demonstrate the energy harvesting behavior of FO-TEG, lighting of an array of LEDs is demonstrated using artificial vibration and human running.


IEEE Electron Device Letters | 2016

Comprehensive Analysis of Gate-Induced Drain Leakage in Vertically Stacked Nanowire FETs: Inversion-Mode Versus Junctionless Mode

Jae Hur; Byung-Hyun Lee; Min-Ho Kang; Dae-Chul Ahn; Tewook Bang; Seung-Bae Jeon; Yang-Kyu Choi

A comprehensive analysis of the gate-induced drain leakage (GIDL) current of vertically stacked nanowire (VS-NW) FETs was carried out. In particular, two different operational modes of the VS-NW, an inversion mode (IM) and a junctionless mode (JM), were compared. The GIDL current of the JM-FET was considerably smaller than that of the IM-FET, and the reason for the difference was consequently determined by numerical simulations. It was found that the source of the difference between the IM-FET and JM-FET was the difference in source/drain (S/D) doping concentration, where the depletion width becomes the tunneling width, considering a long extension length at the S/D regions. The experimental results showed that the GIDL current of the NW FET was significantly controlled by longitudinal band-to-band tunneling (BTBT), rather than the transverse BTBT, as had been reported in the previous literature.


Scientific Reports | 2016

Logic circuits composed of flexible carbon nanotube thin-film transistor and ultra-thin polymer gate dielectric.

Dongil Lee; Jinsu Yoon; J. G. Lee; Byung-Hyun Lee; Myeong-Lok Seol; Hagyoul Bae; Seung-Bae Jeon; Hyejeong Seong; Sung Gap Im; Sung-Jin Choi; Yang-Kyu Choi

Printing electronics has become increasingly prominent in the field of electronic engineering because this method is highly efficient at producing flexible, low-cost and large-scale thin-film transistors. However, TFTs are typically constructed with rigid insulating layers consisting of oxides and nitrides that are brittle and require high processing temperatures, which can cause a number of problems when used in printed flexible TFTs. In this study, we address these issues and demonstrate a method of producing inkjet-printed TFTs that include an ultra-thin polymeric dielectric layer produced by initiated chemical vapor deposition (iCVD) at room temperature and highly purified 99.9% semiconducting carbon nanotubes. Our integrated approach enables the production of flexible logic circuits consisting of CNT-TFTs on a polyethersulfone (PES) substrate that have a high mobility (up to 9.76 cm2 V−1 sec−1), a low operating voltage (less than 4 V), a high current on/off ratio (3 × 104), and a total device yield of 90%. Thus, it should be emphasized that this study delineates a guideline for the feasibility of producing flexible CNT-TFT logic circuits with high performance based on a low-cost and simple fabrication process.


Scientific Reports | 2016

Foldable and Disposable Memory on Paper

Byung-Hyun Lee; Dongil Lee; Hagyoul Bae; Hyejeong Seong; Seung-Bae Jeon; Myung-Lok Seol; Jin-Woo Han; M. Meyyappan; Sung Gap Im; Yang-Kyu Choi

Foldable organic memory on cellulose nanofibril paper with bendable and rollable characteristics is demonstrated by employing initiated chemical vapor deposition (iCVD) for polymerization of the resistive switching layer and inkjet printing of the electrode, where iCVD based on all-dry and room temperature process is very suitable for paper electronics. This memory exhibits a low operation voltage of 1.5 V enabling battery operation compared to previous reports and wide memory window. The memory performance is maintained after folding tests, showing high endurance. Furthermore, the quick and complete disposable nature demonstrated here is attractive for security applications. This work provides an effective platform for green, foldable and disposable electronics based on low cost and versatile materials.


Scientific Reports | 2016

Physically Transient Memory on a Rapidly Dissoluble Paper for Security Application

Hagyoul Bae; Byung-Hyun Lee; Dongil Lee; Myeong-Lok Seol; Daewon Kim; Jin-Woo Han; Choong-Ki Kim; Seung-Bae Jeon; Dae-Chul Ahn; Sang-Jae Park; Jun-Young Park; Yang-Kyu Choi

We report the transient memory device by means of a water soluble SSG (solid sodium with glycerine) paper. This material has a hydroscopic property hence it can be soluble in water. In terms of physical security of memory devices, prompt abrogation of a memory device which stored a large number of data is crucial when it is stolen because all of things have identified information in the memory device. By utilizing the SSG paper as a substrate, we fabricated a disposable resistive random access memory (RRAM) which has good data retention of longer than 106 seconds and cycling endurance of 300 cycles. This memory device is dissolved within 10 seconds thus it can never be recovered or replicated. By employing direct printing but not lithography technology to aim low cost and disposable applications, the memory capacity tends to be limited less than kilo-bits. However, unlike high memory capacity demand for consumer electronics, the proposed device is targeting for security applications. With this regards, the sub-kilobit memory capacity should find the applications such as one-time usable personal identification, authentication code storage, cryptography key, and smart delivery tag. This aspect is attractive for security and protection system against unauthorized accessibility.


Nano Letters | 2017

Functional Circuitry on Commercial Fabric via Textile-Compatible Nanoscale Film Coating Process for Fibertronics

Hagyoul Bae; Byung Chul Jang; Hongkeun Park; Soo-Ho Jung; Hye Moon Lee; Jun-Young Park; Seung-Bae Jeon; Gyeongho Son; Il-Woong Tcho; Kyoungsik Yu; Sung Gap Im; Sung-Yool Choi; Yang-Kyu Choi

Fabric-based electronic textiles (e-textiles) are the fundamental components of wearable electronic systems, which can provide convenient hand-free access to computer and electronics applications. However, e-textile technologies presently face significant technical challenges. These challenges include difficulties of fabrication due to the delicate nature of the materials, and limited operating time, a consequence of the conventional normally on computing architecture, with volatile power-hungry electronic components, and modest battery storage. Here, we report a novel poly(ethylene glycol dimethacrylate) (pEGDMA)-textile memristive nonvolatile logic-in-memory circuit, enabling normally off computing, that can overcome those challenges. To form the metal electrode and resistive switching layer, strands of cotton yarn were coated with aluminum (Al) using a solution dip coating method, and the pEGDMA was conformally applied using an initiated chemical vapor deposition process. The intersection of two Al/pEGDMA coated yarns becomes a unit memristor in the lattice structure. The pEGDMA-Textile Memristor (ETM), a form of crossbar array, was interwoven using a grid of Al/pEGDMA coated yarns and untreated yarns. The former were employed in the active memristor and the latter suppressed cell-to-cell disturbance. We experimentally demonstrated for the first time that the basic Boolean functions, including a half adder as well as NOT, NOR, OR, AND, and NAND logic gates, are successfully implemented with the ETM crossbar array on a fabric substrate. This research may represent a breakthrough development for practical wearable and smart fibertronics.


ACS Nano | 2016

Three-Dimensional Fin-Structured Semiconducting Carbon Nanotube Network Transistor.

Dongil Lee; Byung-Hyun Lee; Jinsu Yoon; Dae-Chul Ahn; Jun-Young Park; Jae Hur; Myung-Su Kim; Seung-Bae Jeon; Min-Ho Kang; Kwanghee Kim; Meehyun Lim; Sung-Jin Choi; Yang-Kyu Choi

Three-dimensional (3-D) fin-structured carbon nanotube field-effect transistors (CNT-FETs) with purified 99.9% semiconducting CNTs were demonstrated on a large scale 8 in. silicon wafer. The fabricated 3-D CNT-FETs take advantage of the 3-D geometry and exhibit enhanced electrostatic gate controllability and superior charge transport. A trigated structure surrounding the randomly networked single-walled CNT channel was formed on a fin-like 3-D silicon frame, and as a result, the effective packing density increased to almost 600 CNTs/μm. Additionally, highly sensitive controllability of the threshold voltage (VTH) was achieved using a thin back gate oxide in the same silicon frame to control power consumption and enhance performance. Our results are expected to broaden the design margin of CNT-based circuit architectures for versatile applications. The proposed 3-D CNT-FETs can potentially provide a desirable alternative to silicon based nanoelectronics and a blueprint for furthering the practical use of emerging low-dimensional materials other than CNTs.


RSC Advances | 2016

Controlled anisotropic wetting of scalloped silicon nanogroove

Gun-Hee Kim; Byung-Hyun Lee; Hwon Im; Seung-Bae Jeon; Dae-Won Kim; Myeong-Lok Seol; Hyundoo Hwang; Yang-Kyu Choi

The anisotropic wetting characteristics of scalloped nanogrooves (SNGs) were investigated for the first time. SNGs with various scallop edge angles were fabricated by Bosch deep reactive ion etching (DRIE). The wetting properties of the nanopatterned surfaces were studied in dynamic and static regimes. The anisotropic wettability of the SNGs was successfully employed to control fluid flows in microfluidic channels.

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