Hagyoul Bae

Direct Observation of a Carbon Filament in Water-Resistant Organic Memory.

The memory for the Internet of Things (IoT) requires versatile characteristics such as flexibility, wearability, and stability in outdoor environments. Resistive random access memory (RRAM) to harness a simple structure and organic material with good flexibility can be an attractive candidate for IoT memory. However, its solution-oriented process and unclear switching mechanism are critical problems. Here we demonstrate iCVD polymer-intercalated RRAM (i-RRAM). i-RRAM exhibits robust flexibility and versatile wearability on any substrate. Stable operation of i-RRAM, even in water, is demonstrated, which is the first experimental presentation of water-resistant organic memory without any waterproof protection package. Moreover, the direct observation of a carbon filament is also reported for the first time using transmission electron microscopy, which puts an end to the controversy surrounding the switching mechanism. Therefore, reproducibility is feasible through comprehensive modeling. Furthermore, a carbon filament is superior to a metal filament in terms of the design window and selection of the electrode material. These results suggest an alternative to solve the critical issues of organic RRAM and an optimized memory type suitable for the IoT era.

Logic circuits composed of flexible carbon nanotube thin-film transistor and ultra-thin polymer gate dielectric.

Printing electronics has become increasingly prominent in the field of electronic engineering because this method is highly efficient at producing flexible, low-cost and large-scale thin-film transistors. However, TFTs are typically constructed with rigid insulating layers consisting of oxides and nitrides that are brittle and require high processing temperatures, which can cause a number of problems when used in printed flexible TFTs. In this study, we address these issues and demonstrate a method of producing inkjet-printed TFTs that include an ultra-thin polymeric dielectric layer produced by initiated chemical vapor deposition (iCVD) at room temperature and highly purified 99.9% semiconducting carbon nanotubes. Our integrated approach enables the production of flexible logic circuits consisting of CNT-TFTs on a polyethersulfone (PES) substrate that have a high mobility (up to 9.76u2009cm2 V−1 sec−1), a low operating voltage (less than 4u2009V), a high current on/off ratio (3u2009×u2009104), and a total device yield of 90%. Thus, it should be emphasized that this study delineates a guideline for the feasibility of producing flexible CNT-TFT logic circuits with high performance based on a low-cost and simple fabrication process.

Foldable and Disposable Memory on Paper

Foldable organic memory on cellulose nanofibril paper with bendable and rollable characteristics is demonstrated by employing initiated chemical vapor deposition (iCVD) for polymerization of the resistive switching layer and inkjet printing of the electrode, where iCVD based on all-dry and room temperature process is very suitable for paper electronics. This memory exhibits a low operation voltage of 1.5u2009V enabling battery operation compared to previous reports and wide memory window. The memory performance is maintained after folding tests, showing high endurance. Furthermore, the quick and complete disposable nature demonstrated here is attractive for security applications. This work provides an effective platform for green, foldable and disposable electronics based on low cost and versatile materials.

Self-Curable Gate-All-Around MOSFETs Using Electrical Annealing to Repair Degradation Induced From Hot-Carrier Injection

Device degradation induced by hot-carrier injection was repaired by electrical annealing using Joule heat through a built-in heater in a gate. The concentrated high temperature anneals the gate oxide locally and the degraded device parameters are recovered or further enhanced within a short time of 1 ms. Selecting a proper range of repair voltage is very important to maximize the annealing effects and minimize the extra damages caused by excessive high temperature. The repairing voltage is related to the resistance of the poly-Si gate according to the device scaling.

Physically Transient Memory on a Rapidly Dissoluble Paper for Security Application

We report the transient memory device by means of a water soluble SSG (solid sodium with glycerine) paper. This material has a hydroscopic property hence it can be soluble in water. In terms of physical security of memory devices, prompt abrogation of a memory device which stored a large number of data is crucial when it is stolen because all of things have identified information in the memory device. By utilizing the SSG paper as a substrate, we fabricated a disposable resistive random access memory (RRAM) which has good data retention of longer than 106u2009seconds and cycling endurance of 300 cycles. This memory device is dissolved within 10u2009seconds thus it can never be recovered or replicated. By employing direct printing but not lithography technology to aim low cost and disposable applications, the memory capacity tends to be limited less than kilo-bits. However, unlike high memory capacity demand for consumer electronics, the proposed device is targeting for security applications. With this regards, the sub-kilobit memory capacity should find the applications such as one-time usable personal identification, authentication code storage, cryptography key, and smart delivery tag. This aspect is attractive for security and protection system against unauthorized accessibility.

Functional Circuitry on Commercial Fabric via Textile-Compatible Nanoscale Film Coating Process for Fibertronics

Fabric-based electronic textiles (e-textiles) are the fundamental components of wearable electronic systems, which can provide convenient hand-free access to computer and electronics applications. However, e-textile technologies presently face significant technical challenges. These challenges include difficulties of fabrication due to the delicate nature of the materials, and limited operating time, a consequence of the conventional normally on computing architecture, with volatile power-hungry electronic components, and modest battery storage. Here, we report a novel poly(ethylene glycol dimethacrylate) (pEGDMA)-textile memristive nonvolatile logic-in-memory circuit, enabling normally off computing, that can overcome those challenges. To form the metal electrode and resistive switching layer, strands of cotton yarn were coated with aluminum (Al) using a solution dip coating method, and the pEGDMA was conformally applied using an initiated chemical vapor deposition process. The intersection of two Al/pEGDMA coated yarns becomes a unit memristor in the lattice structure. The pEGDMA-Textile Memristor (ETM), a form of crossbar array, was interwoven using a grid of Al/pEGDMA coated yarns and untreated yarns. The former were employed in the active memristor and the latter suppressed cell-to-cell disturbance. We experimentally demonstrated for the first time that the basic Boolean functions, including a half adder as well as NOT, NOR, OR, AND, and NAND logic gates, are successfully implemented with the ETM crossbar array on a fabric substrate. This research may represent a breakthrough development for practical wearable and smart fibertronics.

Abnormal electrical characteristics of multi-layered MoS2 FETs attributed to bulk traps

Multiple layers of MoS2 are used as channel materials in a type of field-effect transistor (FET). It was found that the hysteresis in transfer curves and low-frequency noise (LFN) characteristics are varied by the number of layers in MoS2 due to the different influences of bulk traps. The LFN characteristics of a FET composed of a bi-layer MoS2 channel, which was passivated with an atomic-layer-deposited (ALD) Al2O3 layer, follow the conventional carrier number fluctuation (CNF) model. However, FETs consisting of multi-layered MoS2 channels (4, 7, 9, and 18 layers) show abnormal LFN characteristics, which substantially deviate from well-established 1/f noise models such as the CNF and Hooges mobility fluctuation models. The bulk traps inside the MoS2 layers are the origin of the abnormal LFN characteristics and the large hysteresis of FETs with multi-layered MoS2 is due to its randomly embedded bulk traps. Secondary ion mass spectrometry (SIMS) confirms the existence of oxygen species that induce the electrical bulk trap in the MoS2 layers.

Investigation of Low-Frequency Noise in Nonvolatile Memory Composed of a Gate- All-Around Junctionless Nanowire FET

Low-frequency noise (LFN) behaviors, characterized with an SONOS-based gate-all-around junctionless nanowire (JLNW), are investigated to determine the suitability of this type of NW as a memory cell structure. LFN exhibits a 1/f-shape and is described by a carrier number fluctuation noise model. It is found that the proposed device structure shows a low level of device-to-device variation and high immunity against Fowler-Nordheim tunneling stress. Due to the centered conduction path in the JLNW device, the impact of correlated mobility fluctuations on the LFN is insignificant. The trapped charge in the nitride layer of the Silicon(Poly-Si)-oxide(SiO2)-nitride(SiNx)-oxide(SiO2)-silicon(Single-crystalline) (SONOS) device also negligibly influences the LFN. The NW width-dependence is clarified in terms of the effects of the oxide trap density and source/drain series resistance under a fresh and a programmed state.

Electrothermal Annealing (ETA) Method to Enhance the Electrical Performance of Amorphous-Oxide-Semiconductor (AOS) Thin-Film Transistors (TFTs)

An electro-thermal annealing (ETA) method, which uses an electrical pulse of less than 100 ns, was developed to improve the electrical performance of array-level amorphous-oxide-semiconductor (AOS) thin-film transistors (TFTs). The practicality of the ETA method was experimentally demonstrated with transparent amorphous In-Ga-Zn-O (a-IGZO) TFTs. The overall electrical performance metrics were boosted by the proposed method: up to 205% for the trans-conductance (gm), 158% for the linear current (Ilinear), and 206% for the subthreshold swing (SS). The performance enhancement were interpreted by X-ray photoelectron microscopy (XPS), showing a reduction of oxygen vacancies in a-IGZO after the ETA. Furthermore, by virtue of the extremely short operation time (80 ns) of ETA, which neither provokes a delay of the mandatory TFTs operation such as addressing operation for the display refresh nor demands extra physical treatment, the semipermanent use of displays can be realized.

Local Electro-Thermal Annealing for Repair of Total Ionizing Dose-Induced Damage in Gate-All-Around MOSFETs

A shift in threshold voltage caused by total ionizing dose (TID) is problematic in the MOSFET, especially in aerospace applications. Unlike traditional methods to minimize damage from TID, in this letter, a novel electro-thermal annealing method to cure the TID-induced damage is demonstrated for the first time. In this concept, the conventional hardening or shielding techniques are not used. In a gate-all-around MOSFET structure, dual gate electrodes were employed as an embedded nanowire heater to generate localized Joule heat, which can anneal insulating layers, including gate oxide and spacer. With the Joule heat, trapped positive charges produced by the TID were neutralized within 200 ms. A damaged device with a radiation-induced threshold voltage shift was repaired to the level of a fresh pristine device.