Shabbir H. Batterywala

Track assignment: a desirable intermediate step between global routing and detailed routing

Routing is one of the most complex stages in the back-end design process. Simple routing algorithms based on two stages of global routing and detailed routing do not offer appropriate opportunities to address problems arising from signal delay, cross-talk and process constraints. An intermediate stage of track assignment between global and detailed routing proves to be an ideal place to address these problems. With this stage it is possible to use global routing information to efficiently address these problems and to aid the detailed router in achieving the wiring completions. In this paper we formulate routing as a three stage process; global routing, track assignment and detailed routing. We describe the intermediate track assignment problem and suggest an efficient heuristic for its solution. We introduce cost metrics to model basic effects arising from connectivity. We discuss extensions to include signal integrity and process constraints. We propose a heuristic based on weighted bipartite matching as a core routine. To improve its performance additional heuristics based on lookahead and segment splitting are also suggested. Experimental results are given to highlight the efficacy of track assignment stage in routing process.

A statistical method for fast and accurate capacitance extraction in the presence of floating dummy fills

Dummy fills are being extensively used to enhance CMP planarity. However presence of these fills can have a significant impact on the values of interconnect capacitances. Accurate capacitance extraction accounting for these dummies is CPU intensive and cumbersome. For one, there are typically hundreds to thousands of dummy fills in a small layout region, which stress the general purpose capacitance extractor. Second, since these dummy fills are not introduced by the designers, it is of no interest for them to see the capacitances to dummy fills in the extraction reports; they are interested in equivalent capacitances associated with signal power and ground nets. Hence extracting equivalent capacitances across nets of interest in the presence of large number of dummy fills is an important and challenging problem. We present a novel extension to the widely popular Monte-Carlo capacitance extraction technique. Our extension handles the dummy fills efficiently. We demonstrate the accuracy and scalability of our approach by two methods: (i) classical and golden technique of finding equivalent interconnect capacitances by eliminating dummy fills through the network reduction method and (ii) comparing extracted capacitances with measurement data from a test chip.

Variance reduction in Monte Carlo capacitance extraction

In this article we address efficiency issues in implementation of Monte Carlo algorithm For 3D capacitance extraction. Error bounds in statistical capacitance estimation are discussed. Methods to tighten them through variance reduction techniques are detailed. Sample values in implementation of Monte Carlo algorithm are completely determined by the first hop in random walk. This in turn facilitates application of variance reduction techniques like importance sampling and stratified sampling to be used effectively. Experimental results indicate average speedup of 16X in simple uniform dielectric technologies, 7.3X in technologies with layers of dielectrics and 4.6X in technologies having conformal dielectrics.

A method to estimate slew and delay in coupled digital circuits

Coupling capacitance has substantial impact on signal delays and arrival times. It is not always correct to de-couple them using the Miller factors of 0 or 2/spl times/. Towards this end, various de-coupling techniques have been studied in the literature. We extend them and suggest their use in static timing analysis. Our approach uses the switching factor based de-coupling approximation idea to compute the impact of coupling capacitors on signal slews and delays. We suggest an iterative table lookup scheme. The slew and delay tables for the library cell elements are looked up to compute slew and arrival times of signals in the presence of coupling capacitors. The method is easy to use with existing static timing analysis tools. It works with slew and delay tables, which are usually available with technology libraries. Other than table lookups, it requires minimal computation of two switching factors per coupling capacitor per iteration. Analysis and HSPICE simulation results are given to support the suggested method.

Impact of Modern Process Technologies on the Electrical Parameters of Interconnects

This paper presents the results obtained from an experimental study of the impact of modern process technologies on the electrical parameters of interconnects. Variations in parasitic capacitances and resistances due to dummy metal fills, chemical mechanical polishing, multiple thin inter-layer dielectrics and trapezoidal conductor cross-sections are presented. Accurate variations in the parasitics are reported for a set of timing critical nets using 3d field solvers for extraction. Results obtained on a set of industrial designs show that the impact of dummy fills and trapezoidal conductor cross-sections are significant

Cell Swapping Based Migration Methodology for Analog and Custom Layouts

Layout migration is an important step in design reuse. This paper presents a cell swapping based methodology to migrate hierarchical layouts from one technology to another. The migrated layouts retain both layout hierarchy and swapped cell sanctity. The proposed methodology swaps cell instances, marks these instances as fixed, builds broken connectivity due to cell swapping, and then uses a variant of hierarchical compaction for layout migration. Specifically, constraints for cells marked as fixed are formulated differently from standard hierarchical compaction. This ensures that such cells are unaltered in the migrated layout. In this work, a layout migration engine is developed that supports hierarchical compaction with cell swapping. Using the aforementioned methodology, industrial designs are migrated across technologies with the layout migration engine.

On Efficient and Robust Constraint Generation for Practical Layout Legalization

Sub-wavelength lithography in modern fabrication processes has resulted in a tremendous increase in the number of design rules. Of these, the context dependent design rules are especially hard to adhere to during manual layout creation. Layout legalization or automatic correction of design rule violation, therefore, has attained prime importance. Layout legalization can be modeled as a modified layout compaction problem. Generation of constraints from a given layout is a crucial step in compaction. In this paper, we propose a systematic framework for constraint generation that identifies context dependent rules and ensures legal layout upon compaction. In addition, we suggest practical schemes for reducing the legalization problem size that results in subsequent efficient solution.

A 3-dimensional FEM Based Resistance Extraction

Accurate extraction of parasitics is an important pre-cursor to timing and signal integrity analysis. In deep sub-micron technologies, the interconnect cross-section areas of metal at various points in a layer are no longer the same -the metal can be etched differently with varying width and spacings and/or the top-surface of the interconnect layer may be non-planar due to chemical mechanical polishing (CMP). Moreover, the cross-sections are also becoming increasingly trapezoidal in nature. In such a scenario, computing resistances using counting squares technique and other two-dimensional methods may no longer be accurate. At the same time, using highly accurate techniques such as a fine-grained finite element method (FEM) may not be feasible due to the large computation time. In this work, a three-dimensional FEM based resistance extractor that is fast and accurate has been implemented and compared with two other extractors, a counting squares based extractor and a meshing based extractor. The key behind this is an efficient domain discretization which is a conformal decomposition of the original geometry

MoM - a process variation aware statistical capacitance extractor

With the advent of newer technologies, the underlying manufacturing processes are becoming more complicated. This results in substantial variations between mask and actual fabricated geometries of the conductors. These variations in geometries can lead to significant differences in the interconnect capacitances computed using mask and actual geometries. The sources for these variations could be many and the variations could be independent or correlated. We present a novel extension to the statistical Monte-Carlo capacitance extractor to take into account the statistical models of these variations. The variations are handled by an additional Monte-Carlo sampling; hence termed Monte-Carlo over Monte-Carlo (MoM). Our technique reports the expected value and the expected spread of the capacitances along with the co-variance among the different capacitances. We demonstrate the correctness, accuracy and scalability of our technique analytically and experimentally.

Efficient Analog/RF Layout Closure with Compaction Based Legalization

Advancements in process technology have resulted in tremendous increase in the number of design rules. This has greatly complicated the task of building design rule clean layouts. While EDA tools aid in layout creation for standard cell based ASICs, the problem remains unsolved for custom, analog and RF circuits. For such circuits, layout designers spend lot of time converting functionally correct schematic circuits into acceptable design rule clean layouts. While techniques have been proposed to remove Design Rule Violations (DRVs) with minimum perturbation to hand crafted layouts, designers still spend lot of time to get to layout closure. In the proposed methodology, designers can quickly draw sparse and possibly design rule unclean layouts and then use a compaction based layout legalization to clean up the DRVs and reduce area. This increases the productivity of layout designers and reduces the turnaround time for layout closure. The proposed technique achieves close to best possible area for a given sparse layout, keeps hard macros unaltered, respects relative positions, and removes all violations of modeled design rules. Reported experimental results suggest that this method can be used to automate layout creation process.