Subramanian Rajagopalan

Impact of Modern Process Technologies on the Electrical Parameters of Interconnects

This paper presents the results obtained from an experimental study of the impact of modern process technologies on the electrical parameters of interconnects. Variations in parasitic capacitances and resistances due to dummy metal fills, chemical mechanical polishing, multiple thin inter-layer dielectrics and trapezoidal conductor cross-sections are presented. Accurate variations in the parasitics are reported for a set of timing critical nets using 3d field solvers for extraction. Results obtained on a set of industrial designs show that the impact of dummy fills and trapezoidal conductor cross-sections are significant

Cell Swapping Based Migration Methodology for Analog and Custom Layouts

Layout migration is an important step in design reuse. This paper presents a cell swapping based methodology to migrate hierarchical layouts from one technology to another. The migrated layouts retain both layout hierarchy and swapped cell sanctity. The proposed methodology swaps cell instances, marks these instances as fixed, builds broken connectivity due to cell swapping, and then uses a variant of hierarchical compaction for layout migration. Specifically, constraints for cells marked as fixed are formulated differently from standard hierarchical compaction. This ensures that such cells are unaltered in the migrated layout. In this work, a layout migration engine is developed that supports hierarchical compaction with cell swapping. Using the aforementioned methodology, industrial designs are migrated across technologies with the layout migration engine.

On Efficient and Robust Constraint Generation for Practical Layout Legalization

Sub-wavelength lithography in modern fabrication processes has resulted in a tremendous increase in the number of design rules. Of these, the context dependent design rules are especially hard to adhere to during manual layout creation. Layout legalization or automatic correction of design rule violation, therefore, has attained prime importance. Layout legalization can be modeled as a modified layout compaction problem. Generation of constraints from a given layout is a crucial step in compaction. In this paper, we propose a systematic framework for constraint generation that identifies context dependent rules and ensures legal layout upon compaction. In addition, we suggest practical schemes for reducing the legalization problem size that results in subsequent efficient solution.

A 3-dimensional FEM Based Resistance Extraction

Accurate extraction of parasitics is an important pre-cursor to timing and signal integrity analysis. In deep sub-micron technologies, the interconnect cross-section areas of metal at various points in a layer are no longer the same -the metal can be etched differently with varying width and spacings and/or the top-surface of the interconnect layer may be non-planar due to chemical mechanical polishing (CMP). Moreover, the cross-sections are also becoming increasingly trapezoidal in nature. In such a scenario, computing resistances using counting squares technique and other two-dimensional methods may no longer be accurate. At the same time, using highly accurate techniques such as a fine-grained finite element method (FEM) may not be feasible due to the large computation time. In this work, a three-dimensional FEM based resistance extractor that is fast and accurate has been implemented and compared with two other extractors, a counting squares based extractor and a meshing based extractor. The key behind this is an efficient domain discretization which is a conformal decomposition of the original geometry

Efficient Analog/RF Layout Closure with Compaction Based Legalization

Advancements in process technology have resulted in tremendous increase in the number of design rules. This has greatly complicated the task of building design rule clean layouts. While EDA tools aid in layout creation for standard cell based ASICs, the problem remains unsolved for custom, analog and RF circuits. For such circuits, layout designers spend lot of time converting functionally correct schematic circuits into acceptable design rule clean layouts. While techniques have been proposed to remove Design Rule Violations (DRVs) with minimum perturbation to hand crafted layouts, designers still spend lot of time to get to layout closure. In the proposed methodology, designers can quickly draw sparse and possibly design rule unclean layouts and then use a compaction based layout legalization to clean up the DRVs and reduce area. This increases the productivity of layout designers and reduces the turnaround time for layout closure. The proposed technique achieves close to best possible area for a given sparse layout, keeps hard macros unaltered, respects relative positions, and removes all violations of modeled design rules. Reported experimental results suggest that this method can be used to automate layout creation process.

2SAT Based Infeasibility Resolution during Design Rule Correction on Layouts with Multiple Grids

Traditionally, automatic design rule correction (DRC) problem is modeled as a linear program with technology rules and design intents modeled as difference constraints under a minimum perturbation objective. However, these linear programs are often infeasible due to conflicts arising from rules and intents, lack of space or due to incomplete modeling. It is then required to identify problematic constraints and either dilute or drop them to make the linear program feasible. In presence of uniform grid and only difference type constraints, a weighted constraint graph is constructed and infeasibilities are detected as positive cycles. However, this approach breaks down in presence of multiple layer specific grids or discrete track patterns. In this paper, we suggest a novel method for Infeasible Constraint Set Identification (ICSI) for such layouts. Our method transforms the constraint set into a Boolean implications set. Since each implication has only two variables, solving the ICSI problem amounts to determining 2-Satisfiability of the implications set. We then suggest various strategies to resolve infeasibilities.

Fixing Double Patterning violations with look-ahead

Double Patterning Technology (DPT) conflicts express themselves as odd cycles of spacing between layout shapes. One way of resolving these is by imposing a large spacing constraint between a pair of shapes participant in an odd cycle. However, this may shrink spacing in other parts of the layout and introduce DRC violations or new DPT conflicts. In this work, we model DPT conflict resolution as a constrained linear optimization problem, look ahead to upfront estimate potential violations and preclude them with additional constraints. We borrow the approach of Satisfiability Modulo Theory (SMT) solvers to simultaneously check satisfiability of linear constraint set and resolution of DPT conflicts. These two are interleaved and feed information to each other to churn out a feasible set of constraints that fixes DPT and DRC violations. We demonstrate the efficacy of the method on layouts at advanced nodes.