Shah M. Jahinuzzaman

A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read Capability

We propose a quad-node ten transistor (10 T) soft error robust SRAM cell that offers differential read operation for robust sensing. The cell exhibits larger noise margin in sub-0.45 V regime and 26% less leakage current than the traditional soft error tolerant 12 T DICE SRAM cell. When compared to a conventional 6 T SRAM cell, the proposed cell offers similar noise margin as the 6 T cell at half the supply voltage, thus significantly saving the leakage power. In addition, the cell exhibits 98% lower soft error rate than the 6 T cell in accelerated neutron radiation tests carried out at TRIUMF on a 32-kb SRAM implemented in 90-nm CMOS technology.

Threshold voltage instability of amorphous silicon thin-film transistors under constant current stress

We investigate the time-dependent shift in the threshold voltage of amorphous silicon thin-film transistor stressed with constant drain current. We observe a nonsaturating power-law time dependence, which is in contrast to the conventional stretched exponential that saturates at prolonged stress time. The result is consistent with the carrier-induced defect creation model and corroborates the nonlinear dependence of the rate of defect creation on the band-tail carrier density.

An Analytical Model for Soft Error Critical Charge of Nanometric SRAMs

Scaling transistor size to the scale of the nanometer coupled with reduction of supply voltage has made SRAMs more vulnerable to soft errors than ever before. The vulnerability has been accentuated by increased variability in device parameters. In this paper, we present an analytical model for critical charge in order to assess the soft error vulnerability of 6T SRAM cell. The model takes into account the dynamic behavior of the cell and demonstrates a simple technique to decouple the nonlinearly coupled storage nodes. Decoupling of storage nodes enables solving associated current equations to determine the critical charge for an exponential noise current. The critical charge model thus developed consists of both NMOS and PMOS transistor parameters. Consequently, the model can estimate critical charge variations due to variability of transistor parameters and manufacturing defects, such as resistive contacts and vias. In addition, the model can serve as a tool to optimize the hibernation voltage of low-power SRAMs or the size of MIM capacitor per cell in order to achieve a target soft error robustness. Critical charge calculated by the model is in good agreement with SPICE simulations for a commercial 90-nm CMOS process with a maximum discrepancy of less than 5%.

A Compact Hybrid Current/Voltage Sense Amplifier With Offset Cancellation for High-Speed SRAMs

A hybrid current/voltage sense amplification scheme is proposed for high speed SRAMs. The scheme includes an offset cancellation technique which makes it robust against the current sense amplifier (CSA) mismatch. The offset cancellation allows for fast open loop operation of the differential CSA. A fourfold reduction of the cell access time is achieved compared to the conventional scheme under similar cell current and bitline capacitance. Thanks to its automatic turn off nature, the proposed CSA incurs zero static power without an auxiliary turn off circuit. The reduction of the charge redistribution on the bitlines offers a low bitline dynamic power consumption as well. In this work, the proposed scheme is rigorously analyzed and compared to the conventional scheme. The analysis is verified using circuit level simulations and compared to the conventional scheme as a reference analytically and using simulations.

TSPC-DICE: A single phase clock high performance SEU hardened flip-flop

This paper presents a true single-phase clock (TSPC) flip-flop that is robust against radiation-induced single event upsets (SEUs) or soft errors. The flip-flop consists of an input stage that uses a single phase clock to pass the data to a storage unit at the positive edge of the clock. The single phase clock enables designing power-efficient and easily-routed clock-tree and reducing the NBTI effect on the setup and hold times. The storage unit consists of the SEU robust dual interlocked cell (DICE), which has four nodes that replicate the data bit and its complement for recovering from a single event transient (SET). Two nodes with the same logic value inside the storage unit drive a C-element at the output. The C-element masks the propagation of any SET from the internal nodes of the storage unit to the output. The proposed flip-flop consists of only 22 transistors, consumes smaller area, and exhibits as much as 12% lower power-delay product when compared with a recently reported SEU robust flip-flop implemented in a commercial 65nm CMOS technology.

Design and Analysis of A 5.3-pJ 64-kb Gated Ground SRAM With Multiword ECC

This paper presents an SRAM architecture employing a multiword-based ECC (MECC) scheme for soft error mitigation and a row virtual ground technique for array leakage reduction. The MECC combines four data words to form a 128 bit composite ECC word, two of which are interleaved in a row to mitigate cosmic neutron-induced multi-bit errors. The use of a composite word reduces the number of check-bits by 68%, however, requires a unique write operation that updates the check-bits by writing one data word while reading the other three data words. The ground potential of the composite word is raised to a nonzero value during retention in order to limit the leakage power consumption. A critical charge-based soft error rate (SER) model is proposed to estimate the resulting increase in the SER. Both the MECC scheme and the SER model are verified by implementing a 64-kb SRAM macro in 90 nm CMOS technology. The SRAM consumes 5.34 pJ energy with a data latency of 3.3 ns, thus showing up to 82% per-bit energy saving and 8x speed improvement over previously reported multiword ECC schemes. Accelerated neutron radiation test of the SRAM confirms 85% soft error correction by the MECC and 90% accuracy of the SER model.

Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model

Nanometric SRAMs are more vulnerable to experiencing particle induced soft error due to lower operating voltages coupled with higher packing density and increased process variations. In this paper, we present a compact model for critical charge of a 6T SRAM cell for estimating the effects of process variations on its soft error susceptibility. The model is based on dynamic behavior of the cell and a simple decoupling technique for the non-linearly coupled storage nodes. The model describes the critical charge in terms of transistor parameters, cell supply voltage, and injected current parameters. Consequently, it enables investigating the spread of critical charge due to process induced variations in these parameters and to manufacturing defects, such as, resistive contacts or vias. In addition, the model can estimate the improvement in critical charge when MIM capacitors are added to the cell in order to improve the soft error robustness. The critical charge calculated by the model is in good agreement with SPICE simulations for a commercial 90 nm CMOS process with a maximum discrepancy of less than 5%.

A multiword based high speed ECC scheme for low-voltage embedded SRAMS

This paper presents a multiword based error correction code (MECC) scheme to mitigate SEUs in low-voltage SRAMs. MECC combines four 32 bit data words to form a composite 128 bit ECC word and uses optimized transmission-gate XOR logic, thus significantly reducing check-bit overhead and error correction time, respectively. Use of composite word warrants a unique write operation where MECC updates checkbits by simultaneously writing one data word and reading the other three data words. Two composite words are interleaved in a row to tackle multi-bit SEU. In addition, the supply voltage of the SRAM is reduced to save leakage and active power. A 64kb SRAM with MECC implemented in 90nm CMOS technology consumes 154 muW leakage power and 375 muW active power at 0.6 V and 100 MHz, showing improved area and speed-power efficiency than conventional single-word ECC and existing multiword ECC schemes.

Dynamic Data Stability in Low-power SRAM Design

SRAM cell stability measurement is traditionally based on static criteria of data stability requiring 3 coincident points in butterfly curves. We introduce dynamic criteria of stability for the cell knowing that the cell operates in a dynamic environment. It reveals that the true noise margin of the cell can be made considerably higher than the SNM once the cell access time is sufficiently shorter than the cell time-constant. This behavior enables enhancing SRAM yield as well as reducing cell operating voltage without compromising reliability. A 40Kb SRAM designed using SVGND scheme exploits the dynamic behavior of the cell in order to increase the stability and reduce the static and dynamic power consumption. The SRAM unit realized in 0.13 mum CMOS consumes 702 muW at 100 MHz during write operation and offers a 27 pA/Cell leakage current.

Dynamic data stability in SRAM cells and its implications on data stability tests

The paper discusses the concept of dynamic data stability in the SRAM cells. It is shown that the criteria for the absolute static data stability in an SRAM cell is a sub-set of its dynamic data stability. Hence, test methods that are based on dynamic stress of the cell have limited success in discovering the defective cells. Hammer test, for example, fails to discover the faults in an SRAM cell when it is data stable in the dynamic sense but not statically data stable. It will be shown that a long cell access time can detect such faults as it reduces the effect of the dynamic data stability. This method can be combined with stressed cell methods to achieve higher accuracy. Simulation results in a 130nm CMOS technology confirm the method with a good success