David Rennie

A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read Capability

We propose a quad-node ten transistor (10 T) soft error robust SRAM cell that offers differential read operation for robust sensing. The cell exhibits larger noise margin in sub-0.45 V regime and 26% less leakage current than the traditional soft error tolerant 12 T DICE SRAM cell. When compared to a conventional 6 T SRAM cell, the proposed cell offers similar noise margin as the 6 T cell at half the supply voltage, thus significantly saving the leakage power. In addition, the cell exhibits 98% lower soft error rate than the 6 T cell in accelerated neutron radiation tests carried out at TRIUMF on a 32-kb SRAM implemented in 90-nm CMOS technology.

Neutron- and Proton-Induced Single Event Upsets for D- and DICE-Flip/Flop Designs at a 40 nm Technology Node

Neutron- and proton-induced single-event upset cross sections of D- and DICE-Flip/Flops are analyzed for designs implemented in a 40 nm bulk technology node. Neutron and proton testing of the flip/flops show only a 30%-50% difference between D- and DICE-Flip/Flop error rates and cross sections. Simulations are used to show that charge sharing is the primary cause for the similar failures-in-time (FIT) rates. Such small improvement in the single-event performance of the DICE implementation over standard D-Flip/Flop designs may warrant careful consideration for the use of DICE designs in 40 nm bulk technologies and beyond.

Single-Event Tolerant Flip-Flop Design in 40-nm Bulk CMOS Technology

In this paper, the radiation response of a single-event tolerant flip-flop design named the Quatro flip-flop is presented. Circuit level simulations on the flip-flop design show 1) the critical charge of the sensitive nodes to be greater than that of DICE flip-flop, 2) the number of sensitive nodes and the sensitive area to be fewer than that of DICE flip-flop. A test-chip designed and fabricated at the 40-nm bulk CMOS technology node consisting of Quatro, DICE, and standard D- flip-flops was used for heavy-ions, neutrons, and alpha particles exposures. The experimental results demonstrate superior performance of the Quatro flip-flop design over conventional DICE and D-flip-flop designs.

Performance, Metastability, and Soft-Error Robustness Trade-offs for Flip-Flops in 40 nm CMOS

In modern CMOS processes, soft errors and metastability are two prominent failure mechanisms. Radiation induced single event upsets, or soft-errors, have become a dominant failure mechanism in sub-100 nm CMOS memory and logic circuits. The effects of metastability have also becoming increasingly significant in high-speed applications implemented in nanometric processes. In this paper the design trade-offs for flip-flops between performance, soft-error robustness and metastability are described. Soft-error robust flip-flops are implemented based on both the DICE cell and the Quatro cell. SPICE simulations are used to characterize the transient performance and metastability robustness, and device level simulations were performed to quantify the soft-error robustness. The flip-flops were fabricated in the TSMC 40 nm process and radiation measurements were performed at several test facilities. The Quatro flip-flop showed improved soft-error robustness and metastability when compared with a reference D flip-flop and a DICE flip-flop.

Design and Analysis of A 5.3-pJ 64-kb Gated Ground SRAM With Multiword ECC

This paper presents an SRAM architecture employing a multiword-based ECC (MECC) scheme for soft error mitigation and a row virtual ground technique for array leakage reduction. The MECC combines four data words to form a 128 bit composite ECC word, two of which are interleaved in a row to mitigate cosmic neutron-induced multi-bit errors. The use of a composite word reduces the number of check-bits by 68%, however, requires a unique write operation that updates the check-bits by writing one data word while reading the other three data words. The ground potential of the composite word is raised to a nonzero value during retention in order to limit the leakage power consumption. A critical charge-based soft error rate (SER) model is proposed to estimate the resulting increase in the SER. Both the MECC scheme and the SER model are verified by implementing a 64-kb SRAM macro in 90 nm CMOS technology. The SRAM consumes 5.34 pJ energy with a data latency of 3.3 ns, thus showing up to 82% per-bit energy saving and 8x speed improvement over previously reported multiword ECC schemes. Accelerated neutron radiation test of the SRAM confirms 85% soft error correction by the MECC and 90% accuracy of the SER model.

Novel Soft Error Robust Flip-Flops in 65nm CMOS

Cosmic neutron-induced single event upsets have become a dominant failure mechanism in sub-100 nm CMOS memory and logic circuits. In this paper two SEU-robust flip-flops are described which are based on a hardened storage cell, known as the Quatro cell. One flip-flop utilizes C2MOS gates while the other utilizes a pulsed-latch architecture. The proposed flip-flops exhibit as much as a 50% improvement in power-delay product when compared with recently reported hardened flip-flops. A test chip containing the proposed flip-flops arranged in a shift register configuration was fabricated in a 65 nm CMOS process. Accelerated neutron radiation testing results show that the proposed flip-flops have excellent soft-error robustness.

A 5-Gb/s CDR Circuit With Automatically Calibrated Linear Phase Detector

This paper presents a 5-Gb/s clock and data recovery (CDR) circuit which implements a calibration circuit to correct static phase offsets in a linear phase detector. Static phase offsets directly reduce the performance of CDR circuits as the incoming data is not sampled at the center of the eye. Process nonidealities can cause static phase offsets in linear phase detectors by adversely affecting the circuits in a way which is difficult to design for, making calibration an attractive solution. Both the calibration algorithm and test chip implementation are described and measured results are presented. The CDR circuit was fabricated in a 0.18-mum, six metal layer standard CMOS process. With a pseudorandom bit sequence of 27 - 1 calibration improved the measured bit error rate from 4.6 x 10-2 to less than 10-13.

Comparative Robustness of CML Phase Detectors for Clock and Data Recovery Circuits

In this paper the robustness of CML based phase detectors is analyzed with respect to the scaling of CMOS processes. Phase detectors are an important part of CDR circuits, which enable high-speed serial data links. As CDR circuits are integrated into monolithic CMOS ICs, their robustness becomes critically important. Three phase detectors are analyzed over corners in three standard CMOS processes: 180nm, 130nm and 90nm. The results of the simulations show that the total variation of the static phase offset increases with scaling for all phase detectors. The presence of a static phase offset is mathematically shown to negatively affect the BER of a CDR circuit. The analysis shows that the DFF binary phase detector has an advantage in terms of robustness however it has performance limitations. Both the Alexander and Hogge phase detector experience significant and increasing variations in static phase offset as the technology scales

Design and analysis of metastable-hardened and soft-error tolerant high-performance, low-power flip-flops

In this paper, detailed analysis is given on the design of metastable-hardened and soft-error tolerant flip-flops while maintaining the basic characteristics of low-power and high-performance. We also propose two new flip-flop designs: pre-discharge soft-error tolerant flip-flop (PDFF-SE) and sense-amplifier transmission-gate soft-error tolerant flip-flop (SATG-SE). Following our main design approach, both PDFF-SE and SATG-SE use a cross-coupled inverter on the critical path in the master-stage to achieve good metastability while generating differential signals to facilitate the usage of the Quatro cell in the slave-stage to protect against soft-errors. PDFF-SE is designed to achieve very high performance with good metastability while SATG-SE is a low-power design also with good metastability. We also introduce two new design metrics, namely the metastability-delay-product (MDP) and the metastability-power-delay-product (MPDP), to analyze the design tradeoffs between metastability, power, and performance. Simulation results in 65nm CMOS technology have shown that both proposed designs achieve significant reduction in MDP and MPDP when compared to other flip-flop architectures analyzed in this work. Monte Carlo simulation results also show that these flip-flops are very robust and reliable against process variations and mismatches.

A Novel Tri-State Binary Phase Detector

In this paper a phase detector is introduced which has a similar phase detector response as the Alexander phase detector. Both the Alexander and proposed phase detector are analyzed with respect to their robustness. The analysis shows that the novel phase detector is more robust against process non-idealities than the Alexander, with a 75% reduction in the variation of static phase offsets. The proposed phase detector also consumes less power and requires less area. A CDR circuit which implements the proposed phase detector was designed and fabricated in a 0.18mum six metal layer standard CMOS process. The fabricated CDR circuit can lock to pseudo-random bit sequences (PRBS) up to 231 - 1 at data rates from 5 - 6.25Gb/s. For a PRBS of 231 - 1 at 6.25Gb/s the measured rms jitter and peak-to-peak jitter were 1.7ps and 11ps.