Melvin A. Breuer

A Knowledge-Based System for Designing Testable VLSI Chips

The complexity of VLSI circuits has increased the need for design for testability (DFT). Numerous techniques for designing more easily tested circuits have evolved over the years, with particular emphasis on built-in testing approaches. What has not evolved is a design methodology for evaluating and making choices among the numerous existing approaches. This article describes efforts to build a knowledge-based expert system for designing testable VLSI chips. A framework for a methodology incorporating structural, behavioral, qualitative, and quantitative aspects of known DFT techniques is introduced. This methodology provides a designer with a systematic DFT synthesis approach. The process of partitioning a design into subcircuits for individual processing is described and a new concept¿I-path¿is used to transfer data from one place in the circult to another. Rules for applying testable design methodologies to circuit partitions and for evaluating the various solutions obtained are also presented. Finally, a case study using a prototype system is described.

Defect and error tolerance in the presence of massive numbers of defects

As scaling approaches the physical limits of devices, we will continue to see increasing levels of process variations, noise, and defect densities. Many applications today can tolerate certain levels of errors resulting from such factors. We introduce a new approach for error tolerance resulting in chips containing only error acceptable for such applications.

The Ballast methodology for structured partial scan design

An efficient partial scan technique called Ballast (balanced structure scant test) is presented. Scan path storage elements (SPSEs) are selected such that the remainder of the circuit has certain desirable testability properties. A complete test set is obtained using combinatorial automatic test pattern generation (ATPG). Some SPSEs may need to be provided with a HOLD mode; their number is minimized by ordering the registers in the scan path and formatting the test patterns appropriately. This methodology leads to a low area overhead and allows 100% coverage of irredundant faults. >

Test generation for crosstalk-induced delay in integrated circuits

Due to technology scaling and increasing clock frequency, problems due to noise effects lead to an increase in design/debugging efforts and a decrease in circuit performance. This paper shows how crosstalk coupling between lines can affect the propagation delay of signals in integrated circuits. A model is presented to evaluate the effect of parasitic coupling crosstalk. Conditions for the creation of the worst-case coupling and propagation of a delayed signal are presented. A test pattern generation algorithm utilizing the above conditions is presented and applied to several example circuits.

Test generation in VLSI circuits for crosstalk noise

This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital combinational circuits. These effects are becoming more prevalent due to short signal switching times and deep submicron circuitry. These noise effects can propagate through a circuit and create a logic error in a latch or at a primary output. We first present a new way for predicting the output waveform produced by an inverter due to a non-square wave pulse at its input. Our modeling technique captures such properties as the amplitude of a pulse and its rise/fall times and the delay through a device. To expedite the computation of the response of a logic gate to an input pulse, we have developed a novel way of modeling such gates by an equivalent inverter. We have developed a mixed-signal test generator that incorporates classical PODEM-like static values as well as dynamic signals such as transitions and pulses, and timing information such as signal arrival times, rise/fall times, and gate delay. We also present a new analog cost function that is used to guide the search process. Comparison of results with SPICE simulations confirms the accuracy of this approach. This paper focuses primarily on crosstalk induced pulses, but these results have been extended to deal with speedup and slowdown effects.

Analytic models for crosstalk delay and pulse analysis under non-ideal inputs

In this paper we develop a general methodology to analyze crosstalk to obtain insight into effects that are likely to cause errors in deep submicron high speed circuits. We focus on crosstalk due to capacitive coupling between a pair of lines. We first consider the case where crosstalk noise manifests as a pulse and characterize the maximum amplitude, width, energy and timing of this pulse. Closed form equations quantifying the dependence of these pulse attributes on the values of circuit parameters and the rise time of the input transition are derived. We also consider how crosstalk causes slowdown (speedup), i.e. increases (decreases) the rise/fall times of signals on coupled lines, when their inputs have transitions in the opposite (same) directions. Expressions relating the slowdown (speedup) to circuit parameters, the rise/fall times of the input transitions, and the skew between the transitions are derived. We show that crosstalk effects can be significantly aggravated by variations in the fabrication process. New design corners are identified for validation of designs that have significant crosstalk effects. Finally, the results of our analysis provide conditions that must be satisfied by a sequence of vectors used for validation of designs as well as post-manufacturing testing of devices in the presence of significant crosstalk.

On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays

Fault-tolerance is undoubtedly a desirable property of any processor array. However, increased design and implementation costs should be expected when fault-tolerance is being introduced into the architecture of a processor array. When the processor array is implemented within a single VLSI chip, these cost increases are directly related to the chip silicon area. Thus, the increase in area should be weighed against the improved performance of the gracefully degrading fault-tolerant processor array. In addition, a larger chip area might reduce the wafer yield to an unaceptable level making the use of fault-tolerant VLSI processor arrays impractical. The objective of this paper is to devise performance measures for the evaluation of the effectiveness and area utilization of various fault-tolerant techniques. Another goal is to analyze the reduction in wafer yield and investigate the possibility of yield enhancement through redundancy.

BALLAST: a methodology for partial scan design

In the proposed partial scan methodology, the scan path is constructed so that the rest of the circuit belongs to a class of circuits called balanced sequential structures. Test patterns for this structure are generated by treating it as being combinational. Each test pattern is applied to the circuit by shifting it into the scan path. holding it constant for a fixed number of clock cycles, loading the test result into the scan path, and then shifting it out. This technique achieves full coverage of all detectable faults with a minimal number of scannable storage elements and using only combinational test pattern generation.<<ETX>>

Testing for Intermittent Faults in Digital Circuits

In this paper we present a few fundamental results related to the problems of characterization and detection of intermittent faults in digital circuits, which, up to now, have been almost totally ignored. This problem is important since in many technologies intermittency is a predominant mode of failure.

A Random and an Algorithmic Technique for Fault Detection Test Generation for Sequential Circuits

Two procedures are presented for generating fault detection test sequences for large sequential circuits. In the adaptive random procedure one can achieve a tradeoff between test generation time, length, and percent of circuit tested. An algorithmic path-sensitizing procedure is also presented. Both procedures employ a three-valued logic system. Some experimental results are given.