Shahriar Rabii

A 1.8-V digital-audio sigma-delta modulator in 0.8-/spl mu/m CMOS

Oversampling techniques based on sigma-delta (/spl Sigma//spl Delta/) modulation offer numerous advantages for the realization of high-resolution analog-to-digital (A/D) converters in low-voltage environment. This paper examines the design and implementation of a CMOS /spl Sigma//spl Delta/ modulator for digital-audio A/D conversion that operates from a single 1.8-V power supply. A cascaded modulator that maintains a large full-scale input range while avoiding signal clipping at internal nodes is introduced. The experimental modulator has been designed with fully differential switched-capacitor integrators employing different input and output common-mode levels and boosted clock drivers in order to facilitate low voltage operation. Precise control of common-mode levels, high power supply noise rejection, and low power dissipation are obtained through the use of two-stage, class A/AB operational amplifiers. At a sampling rate of 4 MHz and an oversampling ratio of 80, an implementation of the modulator in a 0.8-/spl mu/m CMOS technology with metal-to-polycide capacitors and NMOS and PMOS threshold voltages of +0.65 V and -0.75 V, respectively, achieves a dynamic range of 99 dB at a Nyquist conversion rate of 50 kHz. The modulator can operate from supply voltages ranging from 1.5-2.5 V, occupies an active area of 1.5 mm/sup 2/, and dissipates 2.5 mW from a 1.8-V supply.

A 5-GHz CMOS transceiver for IEEE 802.11a wireless LAN systems

A 5-GHz transceiver comprising the RF and analog circuits of an IEEE 802.11a-compliant WLAN has been integrated in a 0.25-/spl mu/m CMOS technology. The IC has 22-dBm maximum transmitted power, 8-dB overall receive-chain noise figure and -112-dBc/Hz synthesizer phase noise at 1-MHz frequency offset.

A 2.5-V sigma-delta modulator for broadband communications applications

Oversampled sigma-delta (EA) modulators offer numerous advantages for the realization of high-resolution analog-to-digital (A/D) converters. This paper explores how oversampling and feedback can be employed in high-resolution /spl Sigma//spl Delta/ modulators to extend the signal bandwidth into the range of several megahertz when the oversampling ratio is constrained by technology limitations. A 2-2-1 cascaded multibit architecture suitable for operation from a 2.5-V power supply is presented, and a linearization technique referred to as partitioned data weighted averaging is introduced to suppress in-band digital-to-analog converter (DAC) errors. An experimental prototype based on the proposed topology has been integrated in a 0.5-/spl mu/m double-poly triple-metal CMOS technology. Fully differential double-sampled switched-capacitor integrators enable the modulator to achieve 95-dB dynamic range at a 4-Msample/s Nyquist conversion rate with an oversampling ratio of 16. The experimental modulator dissipates 150 mW from a 2.5-V supply.

A 5 GHz CMOS transceiver for IEEE 802.11a wireless LAN

A 5 GHz transceiver comprising the RF and analog circuits of an IEEE 802.11a-complaint WLAN using a 0.25 /spl mu/m CMOS technology occupies 22 mm/sup 2/. The IC has 22 dBm maximum transmitted power, 8 dB overall receive-chain noise figure, and -112 dBc/Hz synthesizer phase noise at 1 MHz offset.

A 5GHz CMOS transceiver for IEEE 802.11a wireless LAN

A 5 GHz transceiver comprising the RF and analog circuits of an IEEE 802.11a-complaint WLAN using a 0.25 /spl mu/m CMOS technology occupies 22 mm/sup 2/. The IC has 22 dBm maximum transmitted power, 8 dB overall receive-chain noise figure, and -112 dBc/Hz synthesizer phase noise at 1 MHz offset.

A 2.5 V broadband multi-bit /spl Sigma//spl Delta/ modulator with 95 dB dynamic range

A cascaded multi-bit /spl Sigma//spl Delta/ modulator uses double sampling to achieve a conversion rate of at least 4 MSample/s at an oversampling ratio of 16. Partitioned data-weighted averaging extends the dynamic range to 95 dB. The circuit, integrated in 0.5 /spl mu/m CMOS, dissipates 150 mW from a 2.5 V supply.

Trends Toward Low-Voltage Power Supplies

Two factors, technology scaling and battery life in portable electronics, are accelerating the reduction in the supply voltage used for CMOS VLSI circuits beyond what might be expected from historical trends. While the scaling of transistor dimensions results in dramatic increases in both the speed and density of digital circuits, it also results in a corresponding increase in the electric fields within the device if the supply voltage is held constant. Breakdown considerations thus make it increasingly difficult to sustain the constant supply voltage that has characterized the past two decades of advances in CMOS technology. Moreover, lowering the supply voltage significantly reduces the energy consumed per operation in a digital system.

Power Dissipation in Sigma-Delta A/D Converters

This chapter examines the sources of power dissipation in a ΣΔ modulator and evaluates the relative merits of several circuits suitable for implementing low-power modulators that operate from a low supply voltage. The dominant source of power dissipation is identified as the first integrator in Section 4.1. Section 4.2 examines the power dissipation of several integrator architectures using ideal circuits. The impact of circuit nonidealities on the power dissipation of a switched-capacitor integrator is considered in Section 4.3, and the performance of several amplifier topologies is compared in Section 4.4. The chapter ends with a brief discussion of power dissipation in the decimation filter that is used to remove the out-of-band noise present in the modulator output.

Design of a Low-Voltage, High-Resolution Sigma-Delta Modulator

This chapter discusses the architecture and circuit requirements for a CMOS ΣΔ modulator that provides digital-audio performance when operated from a supply voltage of less than 2 V. The primary performance objective is to achieve a dynamic range of 98-dB (16-bit) for a 25-kHz signal bandwidth, while operating from a single 1.8-V supply with the lowest possible power dissipation. The following chapter describes the circuits used to implement this modulator in a 0.8-μm, double-metal, CMOS technology with poly-to-metal capacitors.

Analog-to-Digital Conversion

This chapter begins with a brief overview of analog-to-digital (A/D) conversion, wherein quantization error is considered for both Nyquist-rate and oversampling A/D converters. A subclass of oversampling converters based on noise-shaping topologies commonly referred to as sigma-delta (ΣΔ), or equivalently delta-sigma (ΔΣ), modulators are then examined. The basic operation of a first-order ΣΔ modulator is described, followed by a consideration of higher-order architectures and architectures employing multibit quantization.