Katelijn Vleugels

A 2.5-V sigma-delta modulator for broadband communications applications

Oversampled sigma-delta (EA) modulators offer numerous advantages for the realization of high-resolution analog-to-digital (A/D) converters. This paper explores how oversampling and feedback can be employed in high-resolution /spl Sigma//spl Delta/ modulators to extend the signal bandwidth into the range of several megahertz when the oversampling ratio is constrained by technology limitations. A 2-2-1 cascaded multibit architecture suitable for operation from a 2.5-V power supply is presented, and a linearization technique referred to as partitioned data weighted averaging is introduced to suppress in-band digital-to-analog converter (DAC) errors. An experimental prototype based on the proposed topology has been integrated in a 0.5-/spl mu/m double-poly triple-metal CMOS technology. Fully differential double-sampled switched-capacitor integrators enable the modulator to achieve 95-dB dynamic range at a 4-Msample/s Nyquist conversion rate with an oversampling ratio of 16. The experimental modulator dissipates 150 mW from a 2.5-V supply.

A 0.7-V 870-

This paper introduces a power-efficient, chopper-stabilized switched-capacitor sigma-delta (SigmaDelta) modulator that combines delayed input feedforward and single-comparator tracking multi-bit quantization to achieve high-precision, low-voltage analog-to-digital (A/D) conversion. An experimental prototype of the proposed architecture has been integrated in a 0.18-mum CMOS technology. The prototype operates from a 0.7-V supply voltage with a sampling rate of 5 MSamples/sec and consumes only 870 muW of total power. The converter achieves a dynamic range of 100 dB, a peak signal-to-noise ratio (SNR) of 100 dB and a peak signal-to-noise and distortion ratio (SNDR) of 95 dB for a 25-kHz signal bandwidth.

\mu

A calibration-free, high-resolution analog-to-digital converter designed for a bioluminescence sensor array employs incremental sigma-delta (ΣΔ) modulation to combine the advantages of oversampling with an input multiplexing capability. The resolution of incremental ΣΔ modulators can be improved significantly by means of a technique similar to extended counting. In the approach proposed in this paper, analog-to-digital conversion is accomplished with a two-step process in which the residual error from a second-order incremental ΣΔ modulator is encoded using a successive approximation ADC. By this means it is possible to achieve enhanced resolution and improved static linearity while maintaining a one-to-one mapping between individual input and output samples. An experimental implementation of the proposed modulator has been integrated in a 0.18-μm CMOS technology. Operating from a 1.8-V supply, it achieves a dynamic range of 90.1 dB and a peak signal-to-noise and distortion ratio (SNDR) of 86.3 dB at a conversion rate of 1 MSample/s, with 38.1-mW power consumption.

W Digital-Audio CMOS Sigma-Delta Modulator

Although SigmaDelta modulators have largely been implemented as discrete-time (DT) circuits, a continuous-time (CT) approach offers significant advantages for realizing high-accuracy A/D converters at signal bandwidths where technology considerations may impose significant constraints. A CT design allows for relaxed amplifier unity-gain frequency and power requirements, which can enable the realization of high-resolution modulators with bandwidths of several MHz or more at low power. It also provides the advantage of inherent anti-aliasing filtering. This paper introduces a hybrid CT/DT SigmaDelta modulator for A/D conversion that combines the benefits of CT and DT circuits, while mitigating the challenges associated with CT design. The second-order first stage of a two-stage cascade is implemented in CT, while the first-order second stage is a DT circuit. An experimental prototype of the proposed modulator, integrated in 0.18-mum CMOS technology, operates from a 1.2-V analog supply to allow for easier migration to a 0.13-mum or 90-nm CMOS technology. The prototype achieves a dynamic range of 77 dB, a peak SNR of 71 dB, a peak SNDR of 67 dB, and worst-case anti-aliasing filtering of 48 dB for a signal bandwidth of 7.5 MHz and a sampling rate of 240 MHz. The total power dissipation is 89 mW, including 63.6 mW of analog power.

A High-Resolution Low-Power Incremental

An RF front-end for a WLAN SoC is implemented in 0.18mum CMOS. It integrates a +20dBm PA, a high-sensitivity LNA, and a T/R switch. The T/R switch incorporates an impedance-transformation network to provide a receive S11 of -15dB at 2.4GHz and a sensitivity of -73dBm for a 54Mb/s 802.11g signal. For 64QAM OFDM at 2.4GHz, the TX EVM is -25dB at an output power of +16dBm.

\Sigma\Delta

A calibration-free, high-resolution ADC designed for bioluminescence sensing employs an extended-counting architecture in which the residual error from a second-order incremental SigmaDelta modulator is encoded using a successive approximation ADC. The ADC has been integrated in 0.18-mum CMOS technology and achieves a dynamic range of 90.1 dB and a peak SNDR of 86.3 dB at a conversion rate of 1MSample/sec with 38 mW power consumption.

ADC With Extended Range for Biosensor Arrays

An 802.11 a/b/g wireless LAN SoC for low-power embedded applications is implemented in a 0.18mum CMOS technology. The IC integrates the RF transceiver, digital PHY and MAC, CPU and host interface. For 64QAM OFDM, the 5GHz/2.4GHz TX EVM is -27.4dB/-27.5dB at an output power of -5.2dBm/-3.5dBm. Overall 5GHz/2.4GHz RX sensitivity is -73dBm/-76dBm at 54Mb/s

A 77-dB Dynamic Range, 7.5-MHz Hybrid Continuous-Time/Discrete-Time Cascaded

A high-precision, low-voltage, low-power SigmaDelta modulator has been designed using a delayed input feedforward architecture and a tracking multi-bit quantizer employing a single comparator. A 0.18-mum CMOS experimental prototype achieves 100 dB of dynamic range, 100-dB peak SNR and 95-dB peak SNDR for a signal bandwidth of 25 kHz, while consuming only 870 muW of total power from a 0.7-V supply at a 5-MHz sampling rate.

\Sigma \Delta

A hybrid ΣΔ modulator combines the anti-aliasing filtering and high sampling rate advantages of a continuous-time first stage with a low-power discrete-time second stage. A 0.18-μm CMOS experimental prototype samples signals at 240 MHz and achieves 77 dB of dynamic range and a peak SNDR of 67 dB for a signal bandwidth of 7.5 MHz, while dissipating 63.6 mW of analog power from a 1.2-V supply.

Modulator

A cascaded multi-bit /spl Sigma//spl Delta/ modulator uses double sampling to achieve a conversion rate of at least 4 MSample/s at an oversampling ratio of 16. Partitioned data-weighted averaging extends the dynamic range to 95 dB. The circuit, integrated in 0.5 /spl mu/m CMOS, dissipates 150 mW from a 2.5 V supply.