David K. Su

Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits

An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate. Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer. Observations indicate that reducing the inductance in the substrate bias is the most effective. Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry. A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed. >

A 5-GHz CMOS transceiver for IEEE 802.11a wireless LAN systems

A 5-GHz transceiver comprising the RF and analog circuits of an IEEE 802.11a-compliant WLAN has been integrated in a 0.25-/spl mu/m CMOS technology. The IC has 22-dBm maximum transmitted power, 8-dB overall receive-chain noise figure and -112-dBc/Hz synthesizer phase noise at 1-MHz frequency offset.

A Digitally Modulated Polar CMOS Power Amplifier With a 20-MHz Channel Bandwidth

This paper presents a CMOS RF power amplifier that employs a digital polar architecture to improve the overall power efficiency when amplifying signals with high linearity requirements. The power amplifier comprises 64 parallel RF amplifiers that are driven by a constant envelope RF phase-modulated signal. The unit amplifiers are digitally activated by a 6-bit envelope code to construct a non-constant envelope RF output, thereby performing a digital-to-RF conversion. In order to suppress the spectral images resulting from the discrete-time to continuous-time conversion of the envelope, the use of oversampling and four-fold linear interpolation is explored. An experimental prototype of the polar amplifier has been integrated in a 0.18- mum CMOS technology, occupies a total die area of 1.8 mm2 , operates at a 1.6-GHz carrier frequency with a channel bandwidth of 20 MHz. For an OFDM signal, it achieves a power-added efficiency of 6.7% with an EVM of - 26.8 dB while delivering 13.6 dBm of linear output power and drawing 145 mA from a 1.7-V supply.

A CMOS oversampling D/A converter with a current-mode semi-digital reconstruction filter

Oversampling digital-to-analog (D/A) converters employing sigma-delta modulation noise shaping and single-bit quantization are attractive for use in digital audio applications because of their relaxed reconstruction filtering requirements and their tolerance of component mismatch. However, the use of a two-level D/A interface results in a large amount of out-of-band quantization noise that typically must be attenuated by a carefully designed analog reconstruction filter. This paper introduces a means of simplifying the reconstruction filter design through the use of a semidigital finite-impulse-response (FIR) filter. In particular, it describes an oversampling D/A converter wherein a current-mode semidigital reconstruction filter is used to implement a multilevel D/A interface that attenuates the out-of-band quantization noise without requiring precise component matching. An experimental implementation of the converter achieves a dynamic range of 94 dB and 72 dB attenuation of out-of-band quantization noise for a baseband of 20 kHz. The prototype converter, which consists of a linear interpolator, a second-order noise shaper, and a 128-tap semidigital FIR filter, dissipates 59 mW from a 5-V supply and occupies an active area of 3 mm/sup 2/ when integrated in a 1.2- mu m digital CMOS technology. >

A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g wireless LAN

A single-chip dual-band tri-mode CMOS transceiver that implements the RF and analog front-end for an IEEE 802.11a/b/g wireless LAN is described. The chip is implemented in a 0.25-/spl mu/m CMOS technology and occupies a total silicon area of 23 mm/sup 2/. The IC transmits 9 dBm/8 dBm error vector magnitude (EVM)-compliant output power for a 64-QAM OFDM signal. The overall receiver noise figure is 5.5/4.5 dB at 5 GHz/2.4 GHz. The phase noise is -105 dBc/Hz at a 10-kHz offset and the spurs are below -64 dBc when measured at the 5-GHz transmitter output.

A low-voltage low-power sigma-delta modulator for broadband analog-to-digital conversion

A cascade of sigma-delta modulator stages that employ a feedforward architecture to reduce the signal ranges required at the integrator inputs and outputs has been used to implement a broadband, high-resolution oversampling CMOS analog-to-digital converter capable of operating from low-supply voltages. An experimental prototype of the proposed architecture has been integrated in a 0.25-/spl mu/m CMOS technology and operates from an analog supply of only 1.2 V. At a sampling rate of 40 MSamples/sec, it achieves a dynamic range of 96 dB for a 1.25-MHz signal bandwidth. The analog power dissipation is 44 mW.

A 0.7-V 870-

This paper introduces a power-efficient, chopper-stabilized switched-capacitor sigma-delta (SigmaDelta) modulator that combines delayed input feedforward and single-comparator tracking multi-bit quantization to achieve high-precision, low-voltage analog-to-digital (A/D) conversion. An experimental prototype of the proposed architecture has been integrated in a 0.18-mum CMOS technology. The prototype operates from a 0.7-V supply voltage with a sampling rate of 5 MSamples/sec and consumes only 870 muW of total power. The converter achieves a dynamic range of 100 dB, a peak signal-to-noise ratio (SNR) of 100 dB and a peak signal-to-noise and distortion ratio (SNDR) of 95 dB for a 25-kHz signal bandwidth.

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A single-chip IEEE 802.11g-compliant WLAN radio that implements all RF, analog, and digital PHY and MAC functions is implemented in a 0.18 /spl mu/m CMOS technology. The IC transmits 4 dBm EVM-compliant output power for a 64QAM OFDM signal. The overall receiver sensitivities are -95 dBm and -73 dBm for data rates 6 Mbit/s and 54 Mbit/s, respectively.

W Digital-Audio CMOS Sigma-Delta Modulator

Digital Phase-Locked Loops (DPLLs), which are amenable to CMOS process scaling, have recently been demonstrated for both wireless and wireline applications as alternatives to conventional analog charge-pump based PLLs [1–4]. This paper presents a calibration-free fractional-N DPLL that uses only an integer-N divider with a time-to-digital converter (TDC) embedded inside the VCO and utilizes a mismatch filtering technique to improve the linearity of the TDC.

An 802.11g WLAN SoC

A 2.4/5 GHz transceiver implements the RF and analog front-end of an IEEE 802.11a/g/b WLAN system in 0.25 /spl mu/m CMOS technology. The IC transmits 9 dBm/8 dBm EVM-compliant output power at 5 GHz/2.4 GHz for a 64QAM OFDM signal. The overall receiver NF is 5.5/4.5 dB at 5/2.4 GHz.