Robert Charles Dockerty

Low-leakage n- and p-channel Silicon-gate FET's with an SiO 2 -Si 3 N 4 -gate insulator

n-channel and p-channel silicon-gate FETs are fabricated using a 300-Å SiO<inf>2</inf>-300-Å Si<inf>3</inf>N<inf>4</inf>gate insulator. These devices have low leakage and are suitable for dynamic FET-memory applications. Very low n-channel leakage is achieved by using an n- or p-doped polycrystalline-silicon field shield. One-device dynamic memory cells exhibit long average retention times: 158 s for the n-channel cell and 34 s for the p-channel cell. An oxygen or steam anneal of the Si<inf>3</inf>N<inf>4</inf>is necessary to prevent a large V<inf>t</inf>shift during bias-temperature stress.

Improved Vt Stability of SNOS FETs by Oxygen Annealing

The threshold voltage stability of p- and n-channel silicon gate FETs is improved by annealing the gate silicon nitride in oxygen or steam prior to deposition of the silicon gate. Annealing shifts the threshold voltage negatively by 100-200mV, and lowers the normalized transconductance slightly. Field effect mobility, fast surface state density and junction leakage are not affected by the anneal. Formation of a thin layer of SiO2 plus SiOXNy during annealing increases nitride resistivity and reduces the threshold voltage shift due to charge storage at the oxide-nitride interface.