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Featured researches published by Shantanu R. Gupta.


high-performance computer architecture | 2013

Illusionist: Transforming lightweight cores into aggressive cores on demand

Amin Ansari; Shuguang Feng; Shantanu R. Gupta; Josep Torrellas; Scott A. Mahlke

Power dissipation limits combined with increased silicon integration have led microprocessor vendors to design chip multiprocessors (CMPs) with relatively simple (lightweight) cores. While these designs provide high throughput, single-thread performance has stagnated or even worsened. Asymmetric CMPs offer some relief by providing a small number of high-performance (aggressive) cores that can accelerate specific threads. However, threads are only accelerated when they can be mapped to an aggressive core, which are restricted in number due to power and thermal budgets of the chip. Rather than using the aggressive cores to accelerate threads, this paper argues that the aggressive cores can have a multiplicative impact on single-thread performance by accelerating a large number of lightweight cores and providing an illusion of a chip full of aggressive cores. Specifically, we propose an adaptive asymmetric CMP, Illusionist, that can dynamically boost the system throughput and get a higher single-thread performance across the chip. To accelerate the performance of many lightweight cores, those few aggressive cores run all the threads that are running on the lightweight cores and generate execution hints. These hints are then used to accelerate the execution of the lightweight cores. However, the hardware resources of the aggressive core are not large enough to allow the simultaneous execution of a large number of threads. To overcome this hurdle, Illusionist performs aggressive dynamic program distillation to execute small, critical segments of each lightweight-core thread. A combination of dynamic code removal and phase-based pruning distill programs to a tiny fraction of their original contents. Experiments demonstrate that Illusionist achieves 35% higher single thread performance for all the threads running on the system, compared to a CMP with all lightweight cores, while achieving almost 2X higher system throughput compared to a CMP with all aggressive cores.


Archive | 1995

Clocking scheme for latching of a domino output

Shantanu R. Gupta; Thomas D. Fletcher


Archive | 1994

Method and apparatus for dynamic allocation of multiple buffers in a processor

David B. Papworth; Andrew F. Glew; Glenn J. Hinton; Robert P. Colwell; Michael A. Fetterman; Shantanu R. Gupta; James S. Griffith


Archive | 1994

Method and apparatus for partial and full stall handling in allocation

James S. Griffth; Shantanu R. Gupta; Narayan Hegde


Archive | 1996

Entry allocation in a circular buffer using wrap bits indicating whether a queue of the circular buffer has been traversed

David B. Papworth; Andrew F. Glew; Michael A. Fetterman; Glenn J. Hinton; Robert P. Colwell; Steven J. Griffith; Shantanu R. Gupta; Narayan Hegde


Archive | 1994

Apparatus and method for entry allocation for a resource buffer

Shantanu R. Gupta; James S. Griffith; Glenn J. Hinton


Archive | 1995

Entry allocation in a circular buffer

David B. Papworth; Andrew F. Glew; Michael A. Fetterman; Glenn J. Hinton; Robert P. Colwell; Steven J. Griffith; Shantanu R. Gupta; Narayan Hegde


Archive | 1996

Apparatus and method for entry allocation for a buffer resource utilizing an internal two cycle pipeline

Shantanu R. Gupta; James S. Griffith


Archive | 1993

Entry allocation apparatus and method of same

Shantanu R. Gupta; James S. Griffith


Archive | 1995

Method and apparatus for binding instructions to dispatch ports of a reservation station

James S. Griffith; Shantanu R. Gupta; Glenn J. Hinton

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