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Michael A. Fetterman

Intel

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Publication

Featured researches published by Michael A. Fetterman.

Archive | 1996

Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer

Glenn J. Hinton; David B. Papworth; Andrew F. Glew; Michael A. Fetterman; Robert P. Colwell

Archive | 1994

Circuit and method for scheduling instructions by predicting future availability of resources required for execution

Glenn J. Hinton; Robert W. Martell; Michael A. Fetterman; David B. Papworth; James L. Schwartz

Archive | 1998

Method and apparatus for implementing a set-associative branch target buffer

Bradley D. Hoyt; Glenn I. Hinton; David B. Papworth; Ashwani Kumar Gupta; Michael A. Fetterman; Subramanian Natarajan; Sunil Shenoy; Reynold V. D'Sa

Archive | 1994

Method and apparatus for resolving return from subroutine instructions in a computer processor

Bradley D. Hoyt; Glenn J. Hinton; David B. Papworth; Ashwani Kumar Gupta; Michael A. Fetterman; Subramanian Natarajan; Sunil Shenoy; Reynold V. D'Sa

Archive | 1994

Apparatus and method for handling string operations in a pipelined processor

David B. Papworth; Michael A. Fetterman; Andrew F. Glew; Lawrence O. Smith; Michael M. Hancock; Beth Schultz

Archive | 1994

Method and apparatus for dynamic allocation of multiple buffers in a processor

David B. Papworth; Andrew F. Glew; Glenn J. Hinton; Robert P. Colwell; Michael A. Fetterman; Shantanu R. Gupta; James S. Griffith

Archive | 1997

Dual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unit

Bradley D. Hoyt; Glenn J. Hinton; David B. Papworth; Ashwani Kumar Gupta; Michael A. Fetterman; Subramanian Natarajan; Sunil Shenoy; Reynold V. D'Sa

Archive | 1994

Flag renaming and flag masks within register alias table

Robert P. Colwell; Andrew F. Glew; Atiq Bajwa; Glenn J. Hinton; Michael A. Fetterman

Archive | 1995

Method and apparatus for generating event handler vectors based on both operating mode and event type

Scott Dion Rodgers; Rohit A. Vidwans; Joel Huang; Michael A. Fetterman; Kamla P. Huck

Archive | 1997

Processor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural state

David B. Papworth; Michael A. Fetterman; Andrew F. Glew; Robert P. Colwell; Glenn J. Hinton

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Glenn J. Hinton

Intel

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David B. Papworth

Intel

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Andrew F. Glew

Intel

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Robert P. Colwell

Intel

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Ashwani Kumar Gupta

Intel

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Bradley D. Hoyt

Intel

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Subramanian Natarajan

Intel

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Sunil Shenoy

Intel

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Reynold V. D'Sa

Intel

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Robert W. Martell

Intel

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