Robert P. Colwell

Architecture and implementation of a VLIW supercomputer

Very-long-instruction-word (VLIW) computers achieve high performance by exploiting the fine-grain parallelism present in sequential or vectorizable code. Multiflows /200 and /300 VLIW systems yielded near-supercomputer performance by this means despite the relatively slow (65 ns) clocks. With its much faster clock period (15 ns) and architectural improvements, the new /500 system attains approximately 4-9* the performance of its predecessors. The authors describe the /500 architecture and implementation (i.e. TRACE/500), with special attention paid to the tradeoffs involved in designing very-high-speed VLIWs.<<ETX>>

Latent design faults in the development of Multiflow's TRACE/200

The author recounts some of the more notable design faults that appeared during the development of the Multiflow TRACE/200 series of minisupercomputers. During development of the TRACE, the design errors found appeared to be largely random and uncorrelated. However, it appears that a fairly small set of categories can nearly span the set. These faults fall roughly into a few categories: interface misassumptions, stale-instructions-in-cache, parity-related, designer errors, CAD tools, and parts with defective designs. Specific examples are given for each category, and corrections for these design flaws are mentioned.<<ETX>>

Intel's Formal Verification Experience on the Willamette Development

In some ways, microprocessor design quality has improved tremendously since the’ 70’s and’ 80’s. It was not uncommon in those days to have to respin silicon five or ten times before the device exhibited even basic functionality. Microprocessors were designed by circuit designers directly into schematics, with little pre-silicon functional testing. In the late’ 80’s, register transfer level (RTL) descriptions of CPUs, such as the Intel®486, processor were written, allowing useful pre-silicon validation to be performed. This validation was primarily black-box assembly tests written by humans, and it worked because the CPUs were simple designs that could be controlled and observed directly from such tests. Later CPUs required much more intensive pre-silicon efforts, including random code testing and massive amounts of simulation cycles, to get around human limitations on test writing productivity and insufficient imagination in knowing where to look for bugs. Modern designs (’90’s until present) often run operating systems successfully on first silicon, despite having microarchitectures that are orders of magnitude more complicated than their predecessors.

Intel's college hiring methods and recent results

The Intel Corporation hires large numbers of new college graduates. It has an organized process for managing that hiring, and for evaluating their performance as employees. This paper describes the interview process used by one of Intels large design teams, comparing its outcomes to the actual performance history from 1994-1998.

A VLIW architecture for a trace scheduling compiler

Very Long Instruction Word (VLIW) architectures were promised to deliver far more than the factor of two or three that current architectures achieve from overlapped execution. Using a new type of compiler which compacts ordinary sequential code into long instruction words, a VLIW machine was expected to provide from ten to thirty times the performance of a more conventional machine built of the same implementation technology.Multiflow Computer, Inc., has now built a VLIW called the TRACETM along with its companion Trace SchedulingTM compacting compiler. This new machine has fulfilled the performance promises that were made. Using many fast functional units in parallel, this machine extends some of the basic Reduced-Instruction-Set precepts: the architecture is load/store, the microarchitecture is exposed to the compiler, there is no microcode, and there is almost no hardware devoted to synchronization, arbitration, or interlocking of any kind (the compiler has sole responsibility for runtime resource usage).This paper discusses the design of this machine and presents some initial performance results.