Shao-Yu Chou

A 0.6V 45nm adaptive dual-rail SRAM compiler circuit design for lower VDD_min VLSIs

A 0.6 V 45 nm dual-rail SRAM design utilizing an adaptive voltage regulator targeting for an SRAM compiler application is proposed for the first time. The proposed work describes an adaptive mechanism to generate a cell-Vdd (CVDD), which tracks a certain voltage offset with respect to logic-Vdd (VDD), and provides a mean to lower the VDD down to 0.6 V. To relax IR-drop constraints of CVDD power routings in P&R flow, shifting bite-line (BL) pre-charge power supply from CVDD to VDD is adopted in this work. This also avoids the congestion of the VDD and CVDD power mesh. A 45 nm test chip has demonstrated that these concepts successfully can push the VDD_min down to 0.6 V, which is > 250 mV lower than the conventional single-rail SRAMpsilas.

Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40 nm Fully Functional Embedded SRAM

This paper proposes schemes for the direct measurement of bit-line (BL) voltage swing, sense amplifier (SA) offset voltage, and word-line (WL) pulse width, demonstrated in a 40 nm CMOS 32 kb fully functional SRAM macro with <;2% area penalty. This is the first such scheme to enable the optimal tuning of WL-pulse (WLP) width according to on-site measurement results for BL voltage swing, dynamic read stability, and write margin, all of which depend on WLP width. It also eliminates the need for additional margins related to BL voltage swing, which has conventionally been required to ensure adequate tolerances against simulation errors and inaccurate estimation of SA offset voltage. This opens up possibilities for a more aggressive approach to deal with WLP width instead of only ensuring the target BL voltage swing.