Jui-Jen Wu

A Large

Nanometer SRAM cannot achieve lower VDDmin due to read-disturb, half-select disturb and write failure. This paper demonstrates quantitative performance advantages of a zigzag 8T-SRAM (Z8T) cell over the decoupled single-ended sensing 8T-SRAM (DS8T) with write-back schemes, which was previously recognized as the most area-efficient cell under large σVTH/VDD conditions. Since Z8T uses only 1T for each decoupled read-port, faster 2T differential sensing (D2S) can be implemented within the same area as the single-ended DS8T. Thanks to D2S, Z8T cell enables much faster R/W speed at VDDmin than DS8T. For the same VDDmin/speed, Z8T reduces the cell area by 15%. The Z8T 32 Kb macro is 14% smaller area and 53% faster than DS8T cells. Three macros were fabricated using foundry provided 65 nm low-power and 90 nm generic processes. The measured VDDmin for a 65 nm 256-row 32 Kb and a 32-row 4 Kb macro are 430 mV and 250 mV respectively. The measured VDDmin for a 90 nm 256-row 64 Kb macro is 230 mV.

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Due to global and local process variations, on-chip SRAM suffers failures at a low supply voltage (VDD). This study proposes a differential data-aware power-supplied D2 AP 8T SRAM cell to address the stability and trade-off-issues between write and half-select accesses that still remain in the conventional 8T and 6T cells. Powered by its bitline pair, the proposed 8T cell applies differential data-aware-supplied voltages to its cross-coupled inverters to increase both stability margins for write and half-select accesses. A boosted bitline scheme also improves the read cell current. Two 39 Kb SRAM macros, D2 AP-8T and conventional 8T, with the same peripheral circuits were fabricated on the same testchip with 45 nm and 40 nm processes. The measured VDDmin for the D2 AP-8T macro is 240 mV-200 mV lower than that of the conventional 8T macro across lots, wafers and dies.

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Resistive RAM (ReRAM) is a promising nonvolatile memory with low write energy, logic-process compatibility, and compact cell area. The 1T1R ReRAM [1-3] fits embedded applications requiring fast read (RD) access time (T_AC) and low RD-V_DDMIN, particularly for devices powered by batteries or energy harvesters. The cross-point ReRAM [4-6] is meant for high capacities with high RD-V_DDMIN and slow T_AC. As devices shrink, ReRAMs have higher cell resistance (R) and greater variations in write time and R, which reduces the R-ratio (R_H/R_L) between the high-R state (HRS, R_H) and low-R state (LRS, R_L). ReRAM also have a high R_L, which enables a larger voltage drop across ReRAM to reduce write voltage and cell-switch (CS) size. Thus, ReRAM macro designs suffer: (1) small sensing margin (SM), limited RD-V_DDMIN, and slow T_AC due to high-R_L and small R-ratio; (2) increase in energy due to large set DC-current (I_DC-SET) resulting from wide set-time (T_SET) distribution. This study develops a swing-sample-andcouple (SSC) voltage-mode sense amplifier (VSA) to overcome (1), enabling 1.8× greater SM for lower RD-V_DDMIN and 1.7× faster T_AC across various V_DD, compared to conventional differential-input (CD) VSAs. To reduce >99% set energy, we use a 4T self-boost-write-termination (SBWT) scheme to cut off I_DC-SET of faster-T_SET devices, with an area penalty below 0.5%. A fabricated 28nm 1Mb ReRAM macro achieves T_AC = 404ns at V_DD = 0.27V and confirms the I_DC-SET cut-off by SBWT.

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A 0.6 V 45 nm dual-rail SRAM design utilizing an adaptive voltage regulator targeted for the SRAM compiler application is proposed for the first time. The proposed work describes an adaptive mechanism to generate cell-Vdd (CVDD), which tracks a certain voltage offset with respect to the logic-Vdd (VDD). This dual-rail solution provides a mean to lower the VDD down to 0.6 V. In this work, the bit-line (BL) is precharged to VDD instead of CVDD. The benefits of such design choice include the relaxation of the IR-drop constraints on the CVDD power mesh routing for P&R flow, and the quick recovery time for the BL to exit the leakage saving mode and precharge to full rail. This implementation can also reduce the congestion of the VDD and CVDD power mesh. A 45 nm test chip demonstrates that these concepts successfully push the minimum operational logic-Vdd voltage level (VDD_min) down to 0.6 V, which is more than 250 mV lower than the conventional single-rail SRAMs.

/VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme

This paper demonstrates for the first time quantitative performance advantages of a zigzag 8T-SRAM (Z8T) cell over the decoupled single-ended sensing 8T-SRAM (DS8T) with write-back schemes, which was previously recognized as the most area-efficient cell under large σVTH/VDD conditions. Since Z8T uses only 1T for each decoupled read-port, faster 2T differential sensing (D2S) can be implemented within the same area as the single-ended DS8T. Thanks to D2S, Z8T cell enables much faster R/W speed at VDDmin than DS8T. For the same VDDmin/speed, Z8T save the cell area by 15%. A fabricated 256-row 32Kb Z8T SRAM, using a 65nm low-power process, is 14% smaller area and 53% faster than DS8T SRAM, and is 430mV lower VDDmin than 6T-SRAM. The 32-row 4Kb Z8T macro achieves 250mV VDDmin.

A Differential Data-Aware Power-Supplied (D

The design of resistive RAM (ReRAM) faces two major challenges: 1) cell area versus write current requirements and 2) cell read current (ICELL) versus read disturbance. This paper proposes ReRAM macros using logic-process-based vertical parasitic-BJT (VPBJT) switches and a corresponding cell array (VPBJT-CA), resulting in a 4.5× macro density compared to conventional NMOS-switch ReRAM for given write current requirements. To overcome temperature-dependent fluctuations in the base-emitter voltage difference (VBE) of VPBJT, we propose a temperature-aware bitline (BL) voltage bias (VBL-R) (TABB) scheme to provide current-mode sensing with 4.7× larger ICELL and 1.6× faster read speeds. Test results of fabricated 0.18 μm 1 Mb and 65 nm 2 Mb VPBJT ReRAM macros confirm the efficacy of the temperature-aware VBL-R, resulting in sub-5-ns random read access times.

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A 0.6 V 45 nm dual-rail SRAM design utilizing an adaptive voltage regulator targeting for an SRAM compiler application is proposed for the first time. The proposed work describes an adaptive mechanism to generate a cell-Vdd (CVDD), which tracks a certain voltage offset with respect to logic-Vdd (VDD), and provides a mean to lower the VDD down to 0.6 V. To relax IR-drop constraints of CVDD power routings in P&R flow, shifting bite-line (BL) pre-charge power supply from CVDD to VDD is adopted in this work. This also avoids the congestion of the VDD and CVDD power mesh. A 45 nm test chip has demonstrated that these concepts successfully can push the VDD_min down to 0.6 V, which is > 250 mV lower than the conventional single-rail SRAMpsilas.

AP) 8T SRAM Cell With Expanded Write/Read Stabilities for Lower VDDmin Applications

Current-mode sense amplifiers (CSA) are commonly used in eNVM, because of their fast read speed at large bitline (BL) loads and small cell read currents. However, conventional CSAs are unable to achieve fast random read access time (TAC), due to significant summed input offsets (IOS-SUM) at read-path. This work proposes a calibration-based asymmetric-voltage-biased CSA (AVB-CSA) to suppress IOS-SUM and enable high-speed sensing without the need for run-time offset-cancellation operations. This work then fabricated two 90 nm AVB-CSA 1 Mb Flash testchips (with and without BL-length test-modes). The AVB-CSA eFlash macros with 512 rows achieved TAC of 3.9 ns at nominal VDD (1.2 V). The BL-length test-mode experiments confirmed a 1.53× improvement in TAC using AVB-CSA with a BL-length of 2048-rows operating at VDD=0.8 V.

19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme

This work proposes bit-line (BL) swing expansion schemes (BL-EXPD), which minimize the product (A*VDDmin) of SRAM cell area (A) and the minimum operation voltage (VDDmin) to the best of our knowledge. The key-enablers to minimize A*VDDmin are: L-shaped 7T cell (L7T) and BL-EXPD. The L7T features: (1) an area efficient cell layout, (2) a read-disturb free decoupled 1T read port (RP), and (3) a half-select disturb free write back scheme[1]. The BL-EXPD enables a 9× larger read-BL (RBL) swing at the 6σ point than that in our previously proposed Z8T[2] and allows single BL sensing to reduce cell area. A fabricated 65nm 256-row BL 32Kb L7T SRAM achieved a 260mV VDDmin. As a result, its A*VDDmin is ~50% lower than for Z8T and conventional 8T SRAM cells [3,4].

A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs

The designs of resistive RAM (ReRAM) macros are limited by 1) a small sensing margin, limited read- VDDmin, and slow read access time (TAC) caused by a high cell-resistance and small cell-resistance-ratio (R-ratio) and 2) poor power integrity and increased energy waste attributable to a large SET dc-current (IDC-SET) resulting from the wide distribution of write (SET)-times (TSET). This study proposes a swing-sample-and-couple (SSC) voltage-mode sense amplifier (VSA) to enable an approximately 1.8+x greater sensing margin for lower VDD min and a 1.7+x faster read speed across a wide VDD range, compared with conventional VSAs. A 4T self-boost-write-termination (SBWT) scheme is proposed to cut off the IDC-SET of devices with a rapid T SET. The SBWT scheme reduces 99+% of the IDC-SET with an area penalty below 0.5%. A fabricated 512 row 28 nm 1 Mb ReRAM macro achieved TAC = 404 ns when VDD=0.27 V and confirmed the IDC-SET cutoff by the SBWT.